Memory cell array of multi-time programmable non-volatile memory
A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.
1. A memory cell array of a multi-time programmable non-volatile memory, the memory cell array is connected with a first coupling line, a second coupling line, a first erase line, a first source line, a second source line, a first bit line and a second bit line, the memory cell array comprising:
a first memory cell, wherein the first memory cell is connected with the first coupling line, the first erase line, the first source line and the first bit line;
a second memory cell, wherein the second memory cell is connected with the first coupling line, the first erase line, the second source line and the second bit line;
a third memory cell, wherein the third memory cell is connected with the second coupling line, the first erase line, the first source line and the first bit line; and
a fourth memory cell, wherein the fourth memory cell is connected with the second coupling line, the first erase line, the second source line and the second bit line;
wherein during a program action, the first coupling line receives a program voltage, and the second coupling line and the first erase line receive a lowest voltage, wherein the first source line and the first bit line receive a first supply voltage, so that the first memory cell is programmed to a first storage state, wherein the second source line and the second bit line receive a second supply voltage, so that the second memory cell is programmed to a second storage state, wherein the program voltage is higher than the second supply voltage, the second supply voltage is higher than the first supply voltage, the first supply voltage is higher than or equal to the lowest voltage.
2. The memory cell array as claimed in claim 1 , wherein the first erase line is connected with a first well region, the first coupling line is connected with a second well region, the second coupling line is connected with a third well region.
3. The memory cell array as claimed in claim 1 , wherein during an erase action, the first coupling line receives the lowest voltage, and the second coupling line and the first erase line receive an erase voltage, wherein the first source line and the first bit line receive the erase voltage, so that the first memory cell is erased to the second storage state, wherein the second source line and the second bit line receive the erase voltage, so that the second memory cell is erased to the second storage state, wherein the erase voltage is higher than the lowest voltage.
4. The memory cell array as claimed in claim 1 , wherein during a read action, the first coupling line and the first erase line receive the first supply voltage, and the second coupling line receives the lowest voltage, wherein the first source line receives the first supply voltage, and the first bit line receives the second supply voltage, so that the first memory cell generates a read current, wherein the second source line and the second bit line receive the first supply voltage, so that the second memory cell does not generate the read current.
5. A memory cell array of a multi-time programmable non-volatile memory, the memory cell array is connected with a first word line, a second word line, a first coupling line, a second coupling line, a first erase line, a first source line, a second source line, a first bit line and a second bit line, comprising:
a first memory cell, wherein the first memory cell is connected with the first word line, the first coupling line, the first erase line, the first source line and the first bit line;
a second memory cell, wherein the second memory cell is connected with the first word line, the first coupling line, the first erase line, the second source line and the second bit line;
a third memory cell, wherein the third memory cell is connected with the second word line, the second coupling line, the first erase line, the first source line and the first bit line; and
a fourth memory cell, wherein the fourth memory cell is connected with the second word line, the second coupling line, the first erase line, the second source line and the second bit line;
wherein during a program action, the first coupling line receives a program voltage, the second coupling line and the first erase line receive a lowest voltage, wherein the first source line and the first bit line receive a first supply voltage, the first word line receives a second supply voltage, so that the first memory cell is programmed to a first storage state, wherein the second source line and the second bit line receive the second supply voltage, the second word line receives the lowest voltage, so that the second memory cell is programmed to a second storage state, wherein the program voltage is higher than the second supply voltage, the second supply voltage is higher than the first supply voltage, the first supply voltage is higher than or equal to the lowest voltage.
6. The memory cell array as claimed in claim 5 , wherein during an erase action, the first coupling line receives the lowest voltage, the second coupling line and the first erase line receive an erase voltage, and the first word line and the second word line receive the first supply voltage, wherein the first source line and the first bit line receive the erase voltage, so that the first memory cell is erased to the second storage state, wherein the second source line and the second bit line receive the erase voltage, so that the second memory cell is erased to the second storage state, wherein the erase voltage is higher than the lowest voltage.
7. The memory cell array as claimed in claim 5 , wherein during a read action, the first coupling line, the second coupling line and the first erase line receive the first supply voltage, the first word line receives the second supply voltage, and the second word line receives the lowest voltage, wherein the first source line receives the first supply voltage, and the first bit line receives the second supply voltage, so that the first memory cell generates a read current, wherein the second source line and the second bit line receive the first supply voltage, so that the second memory cell does not generate the read current.
8. A memory cell array of a multi-time programmable non-volatile memory, the memory cell array is connected with a first coupling line, a second coupling line, a first erase line, a first source line, a second source line, a first bit line and a second bit line, the memory cell array comprising:
a first memory cell, wherein the first memory cell is connected with the first coupling line, the first erase line, the first source line and the first bit line, wherein the first memory cell comprises a first floating gate transistor and a first capacitor, wherein a first terminal of the first capacitor is connected with the first coupling line, and a second terminal of the first capacitor is connected with a floating gate of the first floating gate transistor;
a second memory cell, wherein the second memory cell is connected with the first coupling line, the first erase line, the second source line and the second bit line, wherein the second memory cell comprises ing a second floating gate transistor and a second capacitor, wherein a first terminal of the second capacitor is connected with the first coupling line, and a second terminal of the second capacitor is connected with a floating gate of the second floating gate transistor;
a third memory cell, wherein the third memory cell is connected with the second coupling line, the first erase line, the first source line and the first bit line, wherein the third memory cell comprises a third floating gate transistor and a third capacitor, wherein a first terminal of the third capacitor is connected with the second coupling line, and a second terminal of the third capacitor is connected to with floating gate of the third floating gate transistor; and
a fourth memory cell, wherein the fourth memory cell is connected with the second coupling line, the first erase line, the second source line and the second bit line, wherein the fourth memory cell comprises a fourth floating gate transistor and a fourth capacitor, wherein a first terminal of the fourth capacitor is connected with the second coupling line, and a second terminal of the fourth capacitor is connected with a floating gate of the fourth floating gate transistor,
wherein a body terminal of the first floating gate transistor, a body terminal of the second floating gate transistor, a body terminal of the third floating gate transistor and a body terminal of the fourth floating gate transistor are connected with the first erase line.
9. The memory cell array as claimed in claim 8 , wherein the first memory cell, the second memory cell, the third memory cell and the fourth memory cell adopts memory transistors, each memory transistor of the memory cells includes a charge storage layer, and each body terminal of the memory transistors is connected with the first erase line.