Semiconductor device and method
View Patent ↗An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.
1. A method comprising:
depositing a first inter-layer dielectric (ILD) layer over a source/drain region, the source/drain region adjacent a channel region of a substrate;
forming a gate stack over the channel region of the substrate, top surfaces of the gate stack and the first ILD layer being coplanar;
depositing a second ILD layer over the gate stack and the first ILD layer;
forming a source/drain contact through the second ILD layer, the source/drain contact physically contacting the source/drain region;
forming a gate contact through the second ILD layer, the gate contact physically contacting the gate stack;
recessing the second ILD layer to expose a first sidewall of the source/drain contact and a second sidewall of the gate contact;
forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and
forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.
2. The method of claim 1 , wherein recessing the second ILD layer increases an exposed surface area of the source/drain contact and an exposed surface area of the gate contact by an amount in a range of 100% to 700%.
3. The method of claim 1 , wherein forming the source/drain contact comprises:
forming a lower source/drain contact in the first ILD layer;
recessing the first ILD layer; and
forming an upper source/drain contact in the second ILD layer.
4. The method of claim 1 , wherein forming the source/drain contact comprises:
forming a lower source/drain contact in the first ILD layer;
recessing the lower source/drain contact; and
forming an upper source/drain contact in the second ILD layer.
5. The method of claim 1 , wherein forming the source/drain contact comprises:
forming a continuous conductive feature through the first ILD layer and the second ILD layer.
6. The method of claim 1 , wherein the source/drain contact and the gate contact are formed of a first conductive material, the first conductive feature and the second conductive feature are formed of a second conductive material, and the first conductive material is different from the second conductive material.
7. The method of claim 6 , wherein the first conductive material has a greater work function than the second conductive material.
8. The method of claim 6 further comprising:
implanting an impurity in the first sidewall and the first top surface of the source/drain contact, and in the second sidewall and the second top surface of the gate contact.
9. A method comprising:
forming a gate stack over a channel region of a substrate;
growing a source/drain region adjacent the channel region;
depositing a first inter-layer dielectric (ILD) layer over the source/drain region and the gate stack;
forming a source/drain contact through the first ILD layer, the source/drain contact physically contacting the source/drain region;
forming a gate contact through the first ILD layer, the gate contact physically contacting the gate stack;
recessing the gate contact and the source/drain contact such that a first top surface of the source/drain contact and a second top surface of the gate contact are beneath a top surface of the first ILD layer, wherein recessing the gate contact and the source/drain contact exposes a first sidewall of the first ILD layer and a second sidewall of the first ILD layer;
forming a first conductive feature physically contacting the first sidewall of the first ILD layer and the first top surface of the source/drain contact; and
forming a second conductive feature physically contacting the second sidewall of the first ILD layer and the second top surface of the gate contact.
10. The method of claim 9 , wherein the first top surface of the source/drain contact is convex, and the second top surface of the gate contact is convex.
11. The method of claim 9 further comprising:
depositing a second ILD layer over the source/drain region, the first ILD layer being deposited on the second ILD layer,
wherein forming the source/drain contact comprises:
forming a lower source/drain contact in the second ILD layer;
recessing the second ILD layer; and
forming an upper source/drain contact in the first ILD layer.
12. The method of claim 9 further comprising:
depositing a second ILD layer over the source/drain region, the first ILD layer being deposited on the second ILD layer,
wherein forming the source/drain contact comprises:
forming a lower source/drain contact in the second ILD layer;
recessing the lower source/drain contact; and
forming an upper source/drain contact in the first ILD layer.
13. The method of claim 9 further comprising:
depositing a second ILD layer over the source/drain region, the first ILD layer being deposited on the second ILD layer,
wherein forming the source/drain contact comprises:
forming a continuous conductive feature through the first ILD layer and the second ILD layer.
14. The method of claim 9 , wherein the source/drain contact and the gate contact are formed of a first conductive material, the first conductive feature and the second conductive feature are formed of a second conductive material, and the first conductive material is different from the second conductive material.
15. The method of claim 14 , wherein the first conductive material has a greater work function than the second conductive material.
16. The method of claim 14 further comprising:
implanting an impurity in the first top surface of the source/drain contact, and in the second top surface of the gate contact.
17. A method comprising:
growing a source/drain region adjacent a channel region of a substrate;
depositing a first inter-layer dielectric (ILD) layer over the source/drain region;
forming a source/drain contact through the first ILD layer, the source/drain contact physically contacting the source/drain region;
recessing the first ILD layer to expose a surface of the source/drain contact;
implanting an impurity in an upper region of the first ILD layer and an upper region of the source/drain contact, a lower region of the first ILD layer and a lower region of the source/drain contact remaining undoped, the upper region of the source/drain contact extending between sidewalls of the first ILD layer, the lower region of the source/drain contact extending between the sidewalls of the first ILD layer; and
forming a first conductive feature physically contacting the surface of the source/drain contact exposed by the recessing of the first ILD layer.
18. The method of claim 17 , wherein the surface of the source/drain contact is a sidewall of the source/drain contact.
19. The method of claim 17 , wherein the surface of the source/drain contact is a convex top surface of the source/drain contact.
20. The method of claim 17 , wherein the impurity is implanted after recessing the first ILD layer.