IP Library › Granted Patent US 11,398,438
Granted Patent B2
US 11,398,438 · App. 16/973,091 · Granted Jul 26, 2022

Drive backplane for light-emitting diode, method for preparing same, and display device

Inventor: Haixu Li (Beijing, CN)
Assignee: BOE Technology Group Co., LTD.
H01L23/562H01L25/167H01L27/124H01L27/1259
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Quick Facts
Patent No.
US 11,398,438
App. No.
16/973,091
Granted
Jul 26, 2022
Kind
B2
Abstract

Provided is a drive backplane for a light-emitting diode, including a substrate and a drive structure on the substrate, the drive structure including a thin-film transistor and a stress relief structure; wherein the thin-film transistor includes an active layer on the substrate, a first insulation layer covering the active layer, and a first gate on the first insulation layer; and the stress relief structure is on the first insulation layer and includes a first metal strip on a first side of the first gate and a second metal strip on a second side of the first gate, wherein the first side is opposite to the second side. A method for preparing the light-emitting diode and a display device are further disclosed.

Claims (32)

1. A drive backplane for a light-emitting diode, comprising a substrate and a drive structure on the substrate, the drive structure comprising a thin-film transistor and a stress relief structure; wherein

the thin-film transistor comprises an active layer on the substrate, a first insulation layer covering the active layer, and a first gate on the first insulation layer; wherein the active layer comprises a channel region, a first doped region and a second doped region; and

the stress relief structure is on the first insulation layer and comprises a first metal strip on a first side of the first gate and a second metal strip on a second side of the first gate, wherein the first side is opposite to the second side; wherein an orthographic projection of the first metal strip on the substrate is within an orthographic projection of the first doped region of the active layer on the substrate; and an orthographic projection of the second metal strip on the substrate is within an orthographic projection of the second doped region of the active layer on the substrate.

2. The drive backplane for the light-emitting diode according to claim 1 , wherein the first metal strip and the second metal strip have a rectangular or arched cross-sectional shape in a plane perpendicular to the substrate.

3. The drive backplane for the light-emitting diode according to claim 1 , wherein the first metal strip and the second metal strip are from 2.0 μm to 3.0 μm in width.

4. The drive backplane for the light-emitting diode according to claim 1 , wherein a spacing distance between the first metal strip and the first gate is from 1.5 μm to 2 μm, and a spacing distance between the second metal strip and the first gate is from 1.5 μm to 2 μm.

5. The drive backplane for the light-emitting diode according to claim 1 , wherein the thin-film transistor further comprises a second insulation layer, a third insulation layer, a source electrode, and a drain electrode; wherein

the second insulation layer covers the first gate, the first metal strip and the second metal strip,

the third insulation layer is on the second insulation layer, and is provided with a first via hole and a second via hole, wherein the first doped region is exposed by the first via hole, and the second doped region is exposed by the second via hole; and

the source electrode and the drain electrode are on the third insulation layer, wherein the source electrode connected to the first doped region by the first via hole and the drain electrode connected to the second doped region by the second via hole, such that the first metal strip is disposed between the first gate and the first via hole, and the second metal strip is disposed between the first gate and the second via hole.

6. The drive backplane for the light-emitting diode according to claim 5 , wherein a spacing distance between the first metal strip and the first via hole is from 1.5 μm to 2 μm, and a spacing distance between the second metal strip and the second via hole is from 1.5 μm to 2 μm.

7. The drive backplane for the light-emitting diode according to claim 1 , wherein the first metal strip and the second metal strip extend in an extending direction parallel to the first gate, and lengths of the first metal strip and the second metal strip in the extending direction are greater than or equal to a length of the active layer in the extending direction.

8. A method for preparing a drive backplane for a light-emitting diode, comprising:

forming an active layer on a substrate, wherein the active layer comprises a channel region, a first doped region, and a second doped region;

forming a first insulation layer covering the active layer; and

forming a first gate and a stress relief structure on the first insulation layer by a single patterning process, wherein the stress relief structure comprises a first metal strip on a first side of the first gate and a second metal strip on a second side of the first gate.

9. The method according to claim 8 , wherein the first metal strip and the second metal strip have a rectangular or arched cross-sectional shape in a plane perpendicular to the substrate.

10. The method according to claim 8 , wherein the first metal strip and the second metal strip are from 2.0 μm to 3.0 μm in width.

11. The method according to claim 8 , wherein a spacing distance between the first metal strip and the first gate is from 1.5 μm to 2 μm, and a spacing distance between the second metal strip and the first gate is from 1.5 μm to 2 μm.

12. The method according to claim 8 , wherein the method further comprises:

forming a second insulation layer covering the first gate, the first metal strip, and the second metal strip;

forming a third insulation layer on the second insulation layer, wherein the third insulation layer is provided with a first via hole and a second via hole, the first doped region is exposed by the first via hole, and the second doped region is exposed by the second via hole; and

forming a source electrode and a drain electrode on the third insulation layer, wherein the source electrode is connected to the first doped region by the first via hole, and the drain electrode is connected to the second doped region by the second via hole, such that the first metal strip is disposed between the first gate and the first via hole and the second metal strip is disposed between the first gate and the second via hole.

13. The method according to claim 12 , wherein a spacing distance between the first metal strip and the first via hole is from 1.5 μm to 2 μm, and a spacing distance between the second metal strip and the second via hole is from 1.5 μm to 2 μm.

14. The method according to claim 8 , wherein an orthographic projection of the first metal strip on the substrate is within an orthographic projection of the first doped region of the active layer on the substrate; and an orthographic projection of the second metal strip on the substrate is within an orthographic projection of the second doped region of the active layer on the substrate.

15. The method according to claim 8 , wherein the first metal strip and the second metal strip extend in an extending direction parallel to the first gate, and lengths of the first metal strip and the second metal strip in the extending direction are greater than or equal to a length of the active layer in the extending direction.

16. A display device, comprising a drive backplane for a light-emitting diode; wherein the drive backplane for the light-emitting diode comprises: a substrate and a drive structure on the substrate, the drive structure comprising a thin-film transistor and a stress relief structure; wherein

the thin-film transistor comprises an active layer on the substrate, a first insulation layer covering the active layer, and a first gate on the first insulation layer; wherein the active layer comprises a channel region, a first doped region and a second doped region; and

the stress relief structure is on the first insulation layer and comprises a first metal strip on a first side of the first gate and a second metal strip on a second side of the first gate, wherein the first side is opposite to the second side; wherein an orthographic projection of the first metal strip on the substrate is within an orthographic projection of the first doped region of the active layer on the substrate; and an orthographic projection of the second metal strip on the substrate is within an orthographic projection of the second doped region of the active layer on the substrate.

17. The display device according to claim 16 , wherein the first metal strip and the second metal strip have a rectangular or arched cross-sectional shape in a plane perpendicular to the substrate.

18. The display device according to claim 16 , wherein the first metal strip and the second metal strip are from 2.0 μm to 3.0 μm in width.

19. The display device according to claim 16 , wherein a spacing distance between the first metal strip and the first gate is from 1.5 μm to 2 μm, and a spacing distance between the second metal strip and the first gate is from 1.5 μm to 2 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2020
From: LI, HAIXU
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 054637/0259 →
Priority Claims (1)
CN 201910486911.2 · Jun 5, 2019 · national
Continuity (1)
Related Publication 20210265282A1 · Aug 26, 2021