Polymer layers embedded with metal pads for heat dissipation

1. An integrated circuit structure comprising:

a metal pad;

a passivation layer comprising a portion over the metal pad;

a first polymer layer comprising a portion over the passivation layer;

a first dummy metal pad in the first polymer layer, wherein the first dummy metal pad is electrically floating;

a second dummy metal pad in the first polymer layer;

a second polymer layer over the first polymer layer, over the first dummy metal pad, and over the second dummy metal pad;

a conductive feature in the second polymer layer, the conductive feature electrically coupling the metal pad to the second dummy metal pad; and

a first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the first dummy metal pad.

2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the first dummy metal pad are coplanar with a top surface and a bottom surface, respectively, of the first polymer layer.

3. The integrated circuit structure of claim 1 further comprising:

a package component comprising a surface metallic feature; and

a solder region bonding the surface metallic feature in the package component to the first UBM, wherein the first dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.

4. The integrated circuit structure of claim 1 further comprising:

a third polymer layer between the first polymer layer and the second polymer layer; and

a Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the first dummy metal pad to the first UBM.

5. The integrated circuit structure of claim 1 further comprising:

a second UBM extending into the second polymer layer to electrically couple to the metal pad, wherein the integrated circuit structure is configured to have a current flowing between the second UBM and the metal pad, and wherein the integrated circuit structure is configured not to have any current flowing between the first UBM and the first dummy metal pad.

6. The integrated circuit structure of claim 1 , wherein all sidewalls and an entirety of bottom surfaces of the first dummy metal pad and the second dummy metal pad are in contact with dielectric materials.

7. The integrated circuit structure of claim 1 , wherein the first polymer layer and the second polymer layer are in physical contact with each other.

8. An integrated circuit structure comprising:

a semiconductor substrate;

an interconnect structure over the semiconductor substrate;

a dielectric layer disposed over the interconnect structure;

a first polymer layer over the interconnect structure and over the dielectric layer;

a dummy metal pad extending from a top surface to a bottom surface of the first polymer layer;

an additional dummy metal pad extending from the top surface to the bottom surface of the first polymer layer, an entirety of a bottom surface of the additional dummy metal pad physically contacting the dielectric layer, entireties of sidewall surfaces of the additional dummy metal pad physically contacting the first polymer layer;

a second polymer layer over the first polymer layer; and

a conductive feature extending from the top surface to the bottom surface of the second polymer layer, wherein the conductive feature is electrically coupled to the dummy metal pad, and the dummy metal pad and the conductive feature are both electrically floating.

9. The integrated circuit structure of claim 8 further comprising:

a metal via in the first polymer layer;

a package component comprising a surface metallic feature; and

a solder region electrically connecting the surface metallic feature in the package component to the metal via, with the integrated circuit structure configured to have a current flowing between the metal via and the surface metallic feature, wherein the solder region is further electrically coupled to the additional dummy metal pad.

10. The integrated circuit structure of claim 9 , wherein the dummy metal pad is a terminal feature of an electrical path comprising the dummy metal pad.

11. The integrated circuit structure of claim 9 , wherein the conductive feature, the metal via, and the additional dummy metal pad are electrically grounded, electrically coupled to a positive power supply node, or electrically coupled to a signal voltage.

12. The integrated circuit structure of claim 8 further comprising a conductive plate in the second polymer layer, wherein the conductive plate comprises:

a bottom surface contacting a top surface of the dummy metal pad; and

a top surface contacting a bottom surface of the conductive feature.

13. The integrated circuit structure of claim 8 further comprising:

a third polymer layer between the first polymer layer and the second polymer layer; and

a Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically connects the dummy metal pad to the conductive feature.

14. An integrated circuit structure comprising:

a first package component comprising:

a dummy metal pad extending from a bottom surface to a top surface of a first polymer layer, wherein the dummy metal pad is electrically floating;

a first electrical connector over and electrically coupling to the dummy metal pad;

an additional dummy metal pad extending from the bottom surface to the top surface of the first polymer layer;

a metal via in the first polymer layer, a bottom surface of the metal via being level with a bottom surface of the dummy metal pad and a bottom surface of the additional dummy metal pad; and

a conductive trace, wherein the conductive trace electrically couples the metal via to the additional dummy metal pad; and

a second package component comprising a second electrical connector, wherein the second package component is bonded to the first package component, and the dummy metal pad is electrically coupled to the second electrical connector through the first electrical connector, and wherein the dummy metal pad, the first electrical connector, and the second electrical connector are electrically floating.

15. The integrated circuit structure of claim 14 , wherein the integrated circuit structure is configured not to have any current flowing between the first electrical connector and the dummy metal pad.

16. The integrated circuit structure of claim 14 further comprising:

a semiconductor substrate underlying the dummy metal pad and the metal via; and

an active circuit device at a surface of the semiconductor substrate, wherein the active circuit device is electrically coupled to the metal via.

17. The integrated circuit structure of claim 14 further comprising a second polymer layer over the first polymer layer, wherein the first electrical connector comprises an Under-Bump Metallurgy (UBM) extending into the second polymer layer.

18. The integrated circuit structure of claim 17 further comprising:

a third polymer layer under the second polymer layer and over the first polymer layer; and

an additional conductive trace extending into the third polymer layer, wherein the additional conductive trace electrically couples the dummy metal pad to the first electrical connector.

19. The integrated circuit structure of claim 14 , wherein the first package component comprises a device die, and the second package component is selected from the group consisting of a package substrate, an interposer, and a printed circuit board.

20. The integrated circuit structure of claim 14 , wherein the conductive trace, the metal via, and the additional dummy metal pad are electrically grounded, electrically coupled to a positive power supply node, or electrically coupled to a signal voltage.