IP Library › Granted Patent US 11,398,479
Granted Patent B2
US 11,398,479 · App. 16/649,799 · Granted Jul 26, 2022

Heterogeneous Ge/III-V CMOS transistor structures

Inventors: Willy Rachmady (Beaverton, OR); Abhishek A. Sharma (Hillsboro, OR); Ravi Pillarisetty (Portland, OR); Patrick Morrow (Portland, OR); Rishabh Mehandru (Portland, OR); Aaron D. Lilak (Beaverton, OR); Gilbert Dewey (Beaverton, OR); Cheng-Ying Huang (Hillsboro, OR)
Assignee: Intel Corporation
H01L27/0924H01L29/0669H01L29/20H01L29/41791H01L29/6681H01L2029/7858
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Quick Facts
Patent No.
US 11,398,479
App. No.
16/649,799
Granted
Jul 26, 2022
Kind
B2
Abstract

An integrated circuit includes: a germanium-containing fin structure above a layer of insulation material; a group III-V semiconductor material containing fin structure above the layer of insulation material; a first gate structure on a portion of the germanium-containing fin structure; a second gate structure on a portion of the group III-V semiconductor material containing fin structure; a first S/D region above the layer of insulation material and laterally adjacent to the portion of the germanium-containing fin structure, the first S/D region comprising a p-type impurity and at least one of silicon or germanium; a second S/D region above the layer of insulation material and laterally adjacent to the portion of the group III-V semiconductor material containing fin structure, the second S/D region comprising an n-type impurity and a second group III-V semiconductor material; and a layer comprising germanium between the layer of insulation material and the second S/D region.

Claims (52)

1. An integrated circuit (IC) comprising:

a layer of insulation material;

a first fin structure directly on the layer of insulation material, the first fin structure comprising germanium;

a second fin structure directly on the layer of insulation material, the second fin structure comprising a first group III-V semiconductor material, wherein the first and second fin structures exist in a common plane such that an imaginary horizontal line that passes through the first fin structure also passes through the second fin structure;

a first gate structure on a portion of the first fin structure, the first gate structure including a first gate electrode and a first gate dielectric, the first gate dielectric being between the portion of the first fin structure and the first gate electrode;

a second gate structure on a portion of the second fin structure, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric being between the portion of the second fin structure and the second gate electrode;

a first source or drain region above the layer of insulation material and laterally adjacent to the portion of the first fin structure, the first source or drain region comprising a p-type impurity and at least one of silicon or germanium;

a second source or drain region above the layer of insulation material and laterally adjacent to the portion of the second fin structure, the second source or drain region comprising an n-type impurity and a second group III-V semiconductor material, wherein the second group III-V semiconductor material has a different semiconductor composition than the first group III-V semiconductor material; and

a layer comprising germanium between the layer of insulation material and the second source or drain region.

2. The IC of claim 1 , wherein the layer comprising germanium is part of the second fin structure.

3. The IC of claim 1 , wherein at least part of the layer comprising germanium is under the second gate structure and in contact with the first group III-V semiconductor material.

4. The IC of claim 1 , wherein at least part of the first gate structure surrounds the portion of the first fin structure.

5. The IC of claim 4 , wherein the first gate dielectric and a p-type metal of first gate structure surround the portion of the first fin structure.

6. The IC of claim 1 , wherein at least part of the second gate structure surrounds the portion of the second fin structure.

7. The IC of claim 6 , wherein the second gate dielectric and an n-type metal of second gate structure surround the portion of the second fin structure.

8. The IC of claim 1 , wherein the first gate dielectric and the second gate dielectric are compositionally different, geometrically different, or both compositionally and geometrically different.

9. The IC of claim 1 , wherein the first gate dielectric is on the portion of the first fin structure as well as the layer of insulation material under the portion of the first fin structure, and the second gate dielectric is on the portion of the second fin structure as well as the layer of insulation material under the portion of the second fin structure.

10. The IC of claim 1 , wherein the first gate electrode includes p-type metal, and the second gate electrode includes n-type metal.

11. The IC of claim 1 , wherein the germanium concentration of the first fin structure is greater than 75 atomic percent, and the first and second group III-V semiconductor materials each comprises two or more of gallium, arsenic, indium, and phosphorous.

12. The IC of claim 1 , wherein the first group III-V semiconductor material and the layer comprising germanium have a lattice mismatch no greater than 4%.

13. An integrated circuit (IC) comprising:

a layer of insulation material, the insulation material comprising silicon and oxygen;

a first fin structure above the layer of insulation material, the first fin structure comprising a body of germanium;

a second fin structure above the layer of insulation material, the second fin structure comprising a body of first group III-V semiconductor material, wherein the first and second fin structures exist in a common plane such that an imaginary horizontal line that passes through the first fin structure also passes through the second fin structure;

a first gate structure on a portion of the first fin structure, the first gate structure including a first gate electrode and a first gate dielectric, the first gate dielectric being between the portion of the first fin structure and the first gate electrode, wherein at least part of the first gate structure surrounds the portion of the first fin structure, and wherein the first gate dielectric is on the portion of the first fin structure as well as the layer of insulation material under the portion of the first fin structure;

a second gate structure on a portion of the second fin structure, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric being between the portion of the second fin structure and the second gate electrode, wherein at least part of the second gate structure surrounds the portion of the second fin structure, and wherein the second gate dielectric is on the portion of the second fin structure as well as the layer of insulation material under the portion of the second fin structure;

a first source or drain region above the layer of insulation material and laterally adjacent to the portion of the first fin structure, the first source or drain region comprising a p-type impurity and at least one of silicon or germanium;

a second source or drain region above the layer of insulation material and laterally adjacent to the portion of the second fin structure, the second source or drain region comprising an n-type impurity and a second group III-V semiconductor material, wherein the first group III-V semiconductor material has a different semiconductor composition than the second group III-V semiconductor material; and

a layer comprising germanium between the layer of insulation material and the second source or drain region.

14. The IC of claim 13 , wherein the layer comprising germanium is part of the second fin structure, and/or at least part of the layer comprising germanium is under the second gate structure and in contact with the body of the first group III-V semiconductor material.

15. The IC of claim 13 , wherein the first gate dielectric and a p-type metal of first gate structure surround the portion of the first fin structure, and/or the second gate dielectric and an n-type metal of second gate structure surround the portion of the second fin structure.

16. An integrated circuit (IC) comprising:

a layer of insulation material;

a first fin structure directly on the layer of insulation material, the first fin structure comprising germanium;

a second fin structure directly on the layer of insulation material, the second fin structure comprising a group III-V semiconductor material and a layer comprising germanium between the group III-V semiconductor material and the layer of insulation material, and wherein the first and second fin structures exist in a common plane such that an imaginary horizontal line that passes through the first fin structure also passes through the second fin structure;

a first gate structure on a portion of the first fin structure, the portion of the first fin structure including the germanium, wherein the first gate structure includes a first gate electrode and a first gate dielectric, the first gate dielectric being between the germanium-containing portion of the first fin structure and the first gate electrode;

a second gate structure on a portion of the second fin structure, the portion of the second fin structure including the group III-V semiconductor material, wherein the second gate structure includes a second gate electrode and a second gate dielectric, the second gate dielectric being between the portion of the second fin structure and the second gate electrode;

a first source or drain region above the layer of insulation material and laterally adjacent to the portion of the first fin structure; and

a second source or drain region above the layer of insulation material and laterally adjacent to the portion of the second fin structure, the second source or drain region comprising a second group III-V semiconductor material, wherein the second group III-V semiconductor material has a different semiconductor composition than the group III-V semiconductor material.

17. The IC of claim 16 , wherein:

the first gate structure wraps around the portion of the first fin structure, and the first gate dielectric is on the portion of the first fin structure as well as the layer of insulation material under the portion of the first fin structure; and

the second gate structure wraps around the portion of the second fin structure, and the second gate dielectric is on the portion of the second fin structure as well as the layer of insulation material under the portion of the second fin structure.

18. The IC of claim 16 , wherein the first gate dielectric and the second gate dielectric both include a high-k dielectric material, and the high-k dielectric material of the first gate dielectric is the same as the high-k dielectric material of the second high-k gate dielectric.

19. An integrated circuit (IC) comprising:

a layer of insulation material;

a first fin structure above the layer of insulation material, the first fin structure comprising germanium;

a second fin structure above the layer of insulation material, the second fin structure comprising a first group III-V semiconductor material, wherein the first and second fin structures exist in a common plane such that an imaginary horizontal line that passes through the first fin structure also passes through the second fin structure;

a first gate structure on a portion of the first fin structure, the first gate structure including a first gate electrode and a first gate dielectric, the first gate dielectric being between the portion of the first fin structure and the first gate electrode;

a second gate structure on a portion of the second fin structure, the second gate structure including a second gate electrode and a second gate dielectric, the second gate dielectric being between the portion of the second fin structure and the second gate electrode;

a first source or drain region above the layer of insulation material and laterally adjacent to the portion of the first fin structure, the first source or drain region comprising a p-type impurity and at least one of silicon or germanium;

a second source or drain region above the layer of insulation material and laterally adjacent to the portion of the second fin structure, the second source or drain region comprising an n-type impurity and a second group III-V semiconductor material, wherein the second group III-V semiconductor material has a different semiconductor composition than the first group III-V semiconductor material; and

a layer comprising germanium between the layer of insulation material and the second source or drain region, wherein the first gate dielectric is on the portion of the first fin structure as well as the layer of insulation material under the portion of the first fin structure, and the second gate dielectric is on the portion of the second fin structure as well as the layer of insulation material under the portion of the second fin structure.

Continuity (1)
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