Semiconductor device and method
A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
1. A method comprising:
forming a first fin over a semiconductor substrate, wherein the first fin comprises a first semiconductor material on the substrate and a second semiconductor material on the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material;
forming a shallow trench isolation region adjacent the first fin; and
forming a cap layer over the first fin, wherein forming the cap layer comprises:
performing a pre-clean process to remove a native oxide from exposed surfaces of the first fin;
performing a sublimation process to produce a first precursor; and
performing a deposition process wherein material from the first precursor is deposited on the first fin to form the cap layer, wherein the cap layer is formed in physical contact with side surfaces of the first semiconductor material and side surfaces and a top surface of the second semiconductor material.
2. The method of claim 1 , wherein forming the first fin comprises:
depositing the first semiconductor material over the semiconductor substrate;
depositing the second semiconductor material over the first semiconductor material; and
patterning the second semiconductor material and the first semiconductor material to form the first fin.
3. The method of claim 2 , wherein the first semiconductor material comprises silicon, the second semiconductor material comprises silicon germanium, and the cap layer comprises silicon.
4. The method of claim 1 , wherein the first precursor comprises silane (SiH 4 ).
5. The method of claim 1 , wherein the sublimation process is performed at a temperature of between 50° C. and 300° C. and the deposition process is performed at a temperature of between 200° C. and 450° C.
6. The method of claim 1 , wherein during the deposition process, hydrogen gas is flowed over the first fin at a flow rate of between 0.2 slm and 5 slm.
7. The method of claim 1 , wherein forming the first fin comprises:
epitaxially growing the first semiconductor material on the substrate, the first semiconductor material comprising silicon; and
epitaxially growing the second semiconductor material on the first semiconductor material, the second semiconductor material comprising silicon germanium.
8. A method comprising:
forming an N-well over a substrate;
forming a first semiconductor layer over the N-well, the first semiconductor layer comprising a first semiconductor material;
etching the first semiconductor layer to form a first recess;
forming a second semiconductor layer in the first recess, the second semiconductor layer comprising a second semiconductor material;
etching the first semiconductor layer and the second semiconductor layer to form a first fin comprising the second semiconductor layer and the first semiconductor layer;
forming a cap layer over the first fin, the cap layer comprising a third semiconductor material, wherein forming the cap layer comprises:
removing a native oxide from the second semiconductor layer; and
depositing the cap layer over the first fin from a precursor gas; and
forming a gate stack on the cap layer, wherein a gate dielectric layer of the gate stack is formed on and in contact with the cap layer.
9. The method of claim 8 , wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon germanium.
10. The method of claim 8 , wherein the cap layer is deposited in contact with the first semiconductor material and the second semiconductor material.
11. The method of claim 10 , further comprising forming a shallow trench isolation region in contact with the first fin.
12. The method of claim 8 , wherein the first semiconductor material has a first lattice constant, wherein the second semiconductor material has a second lattice constant greater than the first lattice constant, and wherein the third semiconductor material has a third lattice constant less than the second lattice constant.
13. The method of claim 8 , wherein depositing the cap layer over the first fin forms an intermixed layer between the cap layer and the second semiconductor material, wherein the cap layer comprises silicon, wherein the second semiconductor material comprises silicon germanium, and wherein the intermixed layer comprises silicon germanium having a germanium concentration less than a germanium concentration of the second semiconductor material.
14. A method comprising:
forming a first semiconductor fin, wherein forming the first semiconductor fin comprises:
performing an ion implantation process on a substrate to form an N-well;
epitaxially growing a first semiconductor layer over the N-well, wherein the first semiconductor layer comprises a first monocrystalline material;
epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer comprises a second monocrystalline material; and
forming a cap layer over and in contact with a top surface and sidewalls of the second semiconductor layer, wherein the cap layer comprises a first polycrystalline material; and
forming a gate structure on the first semiconductor fin, wherein forming the gate structure comprises depositing a gate dielectric layer in physical contact with a top surface and side surfaces of the cap layer.
15. The method of claim 14 , wherein forming the cap layer over the second semiconductor layer forms an intermix layer between the second semiconductor layer and the cap layer, the intermix layer comprising materials of the second monocrystalline material and the first polycrystalline material.
16. The method of claim 15 , wherein the intermix layer has a thickness of between 0.5 Å and 20 Å.
17. The method of claim 14 , wherein the first monocrystalline material comprises silicon, wherein the second monocrystalline material comprises silicon germanium, and wherein the first polycrystalline material comprises silicon.
18. The method of claim 14 , further comprising forming a shallow trench isolation (STI) region adjacent the first semiconductor fin and in contact with the N-well, wherein the cap layer is formed after the STI region and wherein the cap layer is formed on the STI region.
19. The method of claim 14 , further comprising forming a second semiconductor fin, wherein forming the second semiconductor fin comprises:
performing an ion implantation process on the substrate to form a P-well; and
epitaxially growing a third semiconductor layer over the P-well, the third semiconductor layer comprising silicon, wherein an uppermost surface of the third semiconductor layer is level with an uppermost surface of the second semiconductor layer, and wherein a lowermost surface of the third semiconductor layer is level with a lowermost surface of the first semiconductor layer.
20. The method of claim 14 , wherein the cap layer further is formed in physical contact with sidewalls of the first semiconductor layer and the N-well.