Single-mask, high-q performance metal-insulator-metal capacitor (MIMCAP)

1. A method of fabricating a metal-insulator-metal (MIM) capacitor, the method comprising:

forming a first electrode plate comprising a first low resistivity material in or on a first dielectric layer adjacent to an interconnect structure that spans first and second metal layers;

forming an insulator stack in electrical contact with the first electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer;

forming a second electrode plate comprising a second low resistivity material on and in electrical contact with the insulator stack; and

forming the MIM capacitor with a planar profile by:

forming conductive lines in the first dielectric layer in a first metal layer, wherein at least one of the conductive lines form the first electrode plate;

forming the etch stop layer over the first dielectric layer and the first electrode plate, and forming a second dielectric layer over the etch stop layer;

forming a capacitor cavity in the second dielectric layer over the first electrode plate laterally across the second metal layer;

forming the high-K dielectric layer on sidewalls and bottom of the capacitor cavity; and

filling a remainder of the capacitor cavity with the second low resistivity material to form the first electrode plate.

2. The method of claim 1 , further comprising encapsulating the conductive lines on the first metal layer with respective barrier layers to form fully clad conductive lines.

3. A method of fabricating a metal-insulator-metal (MIM) capacitor, the method comprising:

forming a first electrode plate comprising a first low resistivity material in or on a first dielectric layer adjacent to an interconnect structure that spans first and second metal layers;

forming an insulator stack in electrical contact with the first electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer;

forming a second electrode plate comprising a second low resistivity material on and in electrical contact with the insulator stack; and

forming the MIM capacitor with a corrugated profile by:

forming floating conductive lines in the first dielectric layer in a first metal layer, wherein at least a portion of the floating conductive lines form the first electrode plate;

performing an air gap etch on the first dielectric layer to form recesses therein that exposes upper portions of the first electrode plate from the first dielectric layer;

forming the etch stop layer over the first dielectric layer and exposed upper portions of the first electrode plate;

forming the high-K dielectric layer over the etch stop layer; and

forming the second electrode plate on the insulator stack by filling in the recesses between the first electrode plate with the second low resistivity material.

4. The method of claim 3 , forming one or more conductive lines over the second electrode plate in a second metal layer.

5. The method of claim 3 , further comprising cladding the first electrode plate with a barrier layer to form a fully clad first electrode plate.

6. The method of claim 3 , further comprising using copper for both the first low resistivity material and the second low resistivity material.

7. An integrated circuit structure, comprising:

a first dielectric layer disposed above a substrate;

an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer; and

a metal-insulator-metal (MIM) capacitor formed adjacent to the interconnect structure, the MIM capacitor having a planar profile comprising:

a bottom electrode plate in the first metal layer formed from a conductive line, wherein the bottom electrode comprises a plurality of two or more floating conductive lines that have portions protruding from a surface of the first dielectric layer and are laterally spaced apart, and a first low resistivity material;

a capacitor cavity formed on the bottom electrode plate in a second dielectric layer laterally across the second metal layer;

an insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer formed on a bottom on the capacitor cavity; and

a top electrode plate disposed on the insulator stack on sides and bottom of the recesses between the two or more floating conductive lines comprising the bottom electrode plate, and comprising a second low resistivity material filling a remainder of the capacitor cavity.

8. The integrated circuit structure of claim 7 wherein the etch stop layer is formed on the bottom electrode plate, the bottom of the capacitor cavity is formed on the etch stop layer, and the high-K dielectric layer is conformally disposed on the etch stop layer and on sidewalls of the capacitor cavity to form the insulator stack.

9. The integrated circuit structure of claim 7 , wherein the capacitor cavity is formed directly on the bottom electrode plate and the high-K dielectric layer is conformally disposed on both the bottom and sidewalls of the capacitor cavity.

10. The integrated circuit structure of claim 7 , wherein a size of the capacitor cavity is greater than approximately 500×500 nanometers and less than 10×10 microns.

11. The integrated circuit structure of claim 7 , wherein a second conductive line is formed on the top electrode plate in a second metal layer.

12. The integrated circuit structure of claim 7 , wherein the capacitor cavity is approximately 5-100 nanometers in thickness.

13. The integrated circuit structure of claim 7 , wherein the bottom electrode plate is fully clad with a barrier layer to form a fully clad bottom electrode plate.

14. The integrated circuit structure of claim 13 , wherein the capacitor cavity is formed on the fully clad bottom electrode plate.

15. The integrated circuit structure of claim 13 , wherein the barrier layer comprises tantalum.

16. An integrated circuit structure, comprising:

a first dielectric layer disposed above a substrate;

an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer; and

a metal-insulator-metal (MIM) capacitor formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure, the MIM capacitor comprising:

a bottom electrode plate comprising a first low resistivity material;

an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and

a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material, wherein the MIM capacitor has a corrugated profile across the first metal layer in which the bottom electrode plate further comprises a plurality of two or more floating conductive lines that have portions protruding from a surface of the first dielectric layer and are laterally spaced apart, wherein the insulator stack is conformally disposed on sides and tops of two or more floating conductive lines protruding from the first dielectric layer and on the surface of the first dielectric layer between the two or more floating conductive lines, and wherein the top electrode plate is disposed on the insulator stack on sides and bottom of the recesses between the two or more floating conductive lines comprising the bottom electrode plate.

17. The integrated circuit structure of claim 16 , wherein the high-K dielectric layer comprises at least one of: hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate.

18. The integrated circuit structure of claim 16 , wherein the insulator stack has a thickness of approximately 50 nm to provide a high-K, low voltage etch stop, and a thickness of up to 200 nm to provide a high voltage etch stop.

19. The integrated circuit structure of claim 16 , wherein the MIM capacitor has a Q factor value selected from: approximately 10,000 at 1 MHz; approximately 1,000 at 100 MHz; approximately 250 at 5 GHz; and approximately 50 at 30 GHz.

20. The integrated circuit structure of claim 16 , wherein the first low resistivity material of the bottom electrode plate is different than the second low resistivity material of the top electrode plate.

21. The integrated circuit structure of claim 16 , wherein the two or more floating conductive lines are laterally spaced apart by approximately 80-160 nm.

22. The integrated circuit structure of claim 16 , wherein the first low resistivity material of the bottom electrode plate is the same as the second low resistivity material of the top electrode plate.

23. The integrated circuit structure of claim 22 , wherein the first low resistivity material and the second low resistivity material comprise copper.