Mitigation of time dependent dielectric breakdown
The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.
1. A method, comprising:
receiving a substrate with a dielectric thereon and comprising a first opening;
forming a first portion of a gate stack comprising a metal stack in the first opening to cover sidewall and bottom surfaces of the first opening, wherein the metal stack forms a second opening in the first opening;
forming spacers in the second opening and in contact with a bottom surface of the second opening so that the first portion of the gate stack is interposed between the spacers and the sidewall surfaces of the first opening, wherein the spacers form a third opening in the second opening; and
depositing a second portion of the gate stack on the first portion and the spacers to fill the third opening, wherein the second portion is in contact with the first portion.
2. The method of claim 1 , wherein forming the first portion of the gate stack comprises:
forming an interfacial layer on the bottom surface of the first opening;
depositing conformally a high-k dielectric on the interfacial layer and the sidewall surfaces of the first opening; and
depositing conformally the metal stack on the high-k dielectric, wherein the metal stack comprises capping layers and work function layers.
3. The method of claim 1 , wherein forming the spacers comprises:
depositing a spacer layer comprising a dielectric material on the first portion of the gate stack; and
etching the spacer layer to remove the spacer layer from top surfaces of the first portion and form the spacers on sidewall surfaces of the first portion.
4. The method of claim 3 , wherein depositing the spacer layer comprises depositing silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), or silicon oxycarbide (SiO x C y ).
5. The method of claim 3 , wherein depositing the spacer layer comprises depositing a silicon-based layer comprising nitrogen.
6. The method of claim 3 , wherein depositing the spacer layer comprises depositing a silicon-based layer comprising carbon.
7. The method of claim 1 , wherein depositing the second portion comprises interposing the spacers between the first portion and the second portion.
8. A structure, comprising:
a substrate;
a dielectric layer on the substrate and comprising an opening;
an interfacial layer in the opening and covering a bottom surface of the opening;
a high-k dielectric conformally deposited on the interfacial layer and sidewall surfaces of the opening, wherein the high-k dielectric is in direct contact with the sidewall surfaces of the dielectric layer;
a gate stack disposed in the opening and comprising a first portion on the high-k dielectric and a second portion on a top surface of the first portion, wherein the first portion is conformal and conformally covers bottom and sidewall surfaces of the opening and comprises a metal stack, and wherein the second portion is in contact with the metal stack; and
a first spacer interposed between sidewall surfaces of the metal stack and sidewall surfaces of the second portion, wherein the first spacer is in contact with a top surface of the metal stack.
9. The structure of claim 8 , wherein the second portion is in physical contact with the top surface of the first portion.
10. The structure of claim 8 , wherein the second portion comprises a metal and the first spacer comprises a dielectric material.
11. The structure of claim 8 , wherein the high-k dielectric is interposed between the first portion of the gate stack and the dielectric layer along the sidewall surfaces of the opening.
12. The structure of claim 8 , wherein the high-k dielectric and the first spacer are laterally separated by the first portion of the gate stack.
13. The structure of claim 8 , wherein the metal stack is conformally deposited on the bottom and sidewall surfaces of the opening.
14. A structure, comprising:
a substrate;
a dielectric layer on the substrate;
an interfacial layer, on the substrate, surrounded by the dielectric layer;
a high-k dielectric conformally deposited on the interfacial layer and sidewall surfaces of the dielectric layer wherein the high-k dielectric is in direct contact with the sidewall surfaces of the dielectric layer; and
a gate stack, on the high-k dielectric, surrounded by the dielectric layer, wherein the gate stack comprises:
a first portion being conformal and conformally covering a top surface and sidewall surfaces of the high-k dielectric, wherein the first portion comprises work function layers;
a spacer structure abutting bottom and sidewall surfaces of the work function layers; and
a second portion abutting the spacer structure and in contact with the work function layers,
wherein the high-k dielectric is interposed between the first portion of the gate stack and the dielectric layer and interposed between the first portion of the gate stack and the substrate.
15. The structure of claim 14 , wherein the first portion comprises one or more capping layers conformally disposed on the high-k dielectric, and the work function layers are conformally disposed on the one or more capping layers.
16. The structure of claim 14 , wherein the spacer structure is interposed between sidewall surfaces of the first portion and sidewall surfaces of the second portion.
17. The structure of claim 14 , wherein the second portion is on a top surface of the first portion.
18. The structure of claim 14 , wherein the spacer structure comprises a dielectric material that separates the first portion from the second portion in a lateral direction.
19. The structure of claim 14 , wherein the spacer structure comprises a silicon-based carbide.
20. The structure of claim 14 , wherein the spacer structure comprises a silicon-based nitride.