Silicon controlled rectifier with a gate electrode for electrostatic discharge protection
A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.
1. A silicon controlled rectifier comprising:
a substrate and a first n-well in the substrate;
a p+ anode region in the first n-well;
a first p-well in the first n-well;
an n+ cathode region in the first p-well;
a field oxide layer over a first portion of the first p-well and a portion of the first n-well adjacent to the first portion of the first p-well; and
a first gate electrode layer over a portion of the field oxide layer and extending over a second portion of the first p-well.
2. The silicon controlled rectifier of claim 1 , further comprising:
a second n-well in the first n-well, wherein the p+ anode region is in the second n-well and the field oxide layer is over a first portion of the second n-well adjacent to the p+ anode region.
3. The silicon controlled rectifier of claim 2 further comprising:
a second p-well in the first p-well, wherein the n+ cathode region is in the second p-well.
4. The silicon controlled rectifier of claim 3 further comprising:
a second gate electrode layer over a portion of the second p-well adjacent to the n+ cathode region.
5. The silicon controlled rectifier of claim 3 , wherein the first gate electrode layer extends over a portion of the second p-well adjacent to the n+ cathode region.
6. The silicon controlled rectifier of claim 2 further comprising:
an n+ doped region in the second n-well.
7. The silicon controlled rectifier of claim 6 further comprising:
a silicide block layer over the p+ anode region and the n+ doped region.
8. The silicon controlled rectifier of claim 6 further comprising:
an isolation region between the n+ doped region and the p+ anode region.
9. The silicon controlled rectifier of claim 6 further comprising:
a second portion of the second n-well between the n+ doped region and the p+ anode region.
10. The silicon controlled rectifier of claim 9 further comprising:
a silicide block layer over the n+ doped region, the p+ anode region and the second portion of the second n-well between the n+ doped region and the p+ anode region.
11. The silicon controlled rectifier of claim 1 further comprising:
a second n-well in the first p-well, wherein the p+ anode region is in the second n-well and the field oxide layer is over a portion of the second n-well adjacent to the p+ anode region.
12. The silicon controlled rectifier of claim 1 , wherein the first gate electrode layer is spaced from the n+ cathode region.
13. A silicon controlled rectifier comprising:
a substrate and a first n-well in the substrate;
a p+ anode region in the first n-well;
a first p-well in the first n-well;
an n+ cathode region in the first p-well;
a field oxide layer over a first portion of the first p-well and a portion of the first n-well adjacent to the first portion of the first p-well;
a first gate electrode layer extending over a second portion of the first p-well and over a portion of the field oxide layer;
a gate dielectric layer between the first gate electrode layer and the second portion of the first p-well; and
a p+ doped region in the first p-well.
14. The silicon controlled rectifier of claim 13 further comprising:
a second p-well in the first p-well, wherein the n+ cathode region and the p+ doped region are in the second p-well.
15. The silicon controlled rectifier of claim 14 further comprising:
a second gate electrode layer over a portion of the second p-well adjacent to the n+ cathode region.
16. The silicon controlled rectifier of claim 15 , wherein a portion of the first p-well is between the first gate electrode layer and the second gate electrode layer.
17. The silicon controlled rectifier of claim 13 further comprising:
a second n-well in the first n-well, wherein the p+ anode region is in the second n-well and the field oxide layer is over a portion of the second n-well adjacent to the p+ anode region.
18. A method of fabricating a silicon controlled rectifier comprising:
forming a first n-well in a substrate;
forming a first p-well in the first n-well;
forming a field oxide layer over a first portion of the first p-well and a portion of the first n-well adjacent to the first portion of the first p-well;
forming a first gate electrode layer over a second portion of the first p-well and over a portion of the field oxide layer;
forming a p+ anode region in the first n-well; and
forming an n+ cathode region in the first p-well.
19. The method of claim 18 , wherein forming the p+ anode region further comprises forming a second n-well in the first n-well and the p+ anode region is formed in the second n-well.
20. The method of claim 19 , wherein forming the n+ cathode region further comprises forming a second p-well in the first p-well and the n+ cathode region is formed in the second p-well.