Semiconductor device
Disclosed is a semiconductor device including a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer. The semiconductor structure includes a first upper surface on which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, an inclined surface connecting the first upper surface and the second upper surface, and a recess formed between the first upper surface and the inclined surface. The recess has a depth less than or equal to 30% of a vertical distance between the first upper surface and the second upper surface.
1. A semiconductor device comprising:
a semiconductor structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer;
a first electrode electrically connected to the first semiconductor layer; and
a second electrode electrically connected to the second semiconductor layer,
wherein,
the semiconductor structure comprises a first upper surface on which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, an inclined surface connecting the first upper surface and the second upper surface, and a recess formed between the first upper surface and the inclined surface, and
the recess has a depth less than or equal to 30% of a vertical distance between the first upper surface and the second upper surface, and
wherein a ratio of a first vertical height from a bottom surface of the semiconductor structure to the second upper surface to a second vertical height from the bottom surface of the semiconductor structure to the first upper surface ranges from 1:0.6 to 1:0.95.
2. The semiconductor device of claim 1 , wherein the first vertical height and the second vertical height have a difference of less than 2 μm.
3. The semiconductor device of claim 1 , wherein a first angle between a horizontal surface and the inclined surface is smaller than a second angle between the horizontal surface and a side surface of the semiconductor structure.
4. The semiconductor device of claim 3 , wherein the first angle ranges from 20° to 80°, and the second angle ranges from 70° to 90°.
5. The semiconductor device of claim 3 , wherein the semiconductor structure comprises a long side surface and a short side surface in plane, and
wherein the long side surface is smaller than 100 μm.
6. The semiconductor device of claim 1 , wherein a width of the inclined surface decreases away from the first upper surface.
7. A semiconductor device comprising:
a semiconductor structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer;
a first electrode electrically connected to the first semiconductor layer; and
a second electrode electrically connected to the second semiconductor layer,
wherein,
the semiconductor structure comprises a first upper surface on which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, an inclined surface connecting the first upper surface and the second upper surface, and a recess formed between the first upper surface and the inclined surface, and
the recess has a depth less than or equal to 30% of a vertical distance between the first upper surface and the second upper surface, and
wherein,
the second semiconductor layer comprises a first sub-semiconductor layer exposed from the first upper surface and a second sub-semiconductor layer disposed on the first sub-semiconductor layer, and
a difference in etching rate between the first sub-semiconductor layer and the second sub-semiconductor layer is less than or equal to 30% under the same etching conditions.
8. The semiconductor device of claim 7 , wherein the first sub-semiconductor layer has a higher etching rate than the second sub-semiconductor layer.
9. The semiconductor device of claim 7 , wherein,
the first sub-semiconductor layer contains GaAs, and
the second sub-semiconductor layer contains AlInP.
10. The semiconductor device of claim 9 , wherein,
the first sub-semiconductor layer further contains In, and
the first sub-semiconductor layer has a higher In composition than the second sub-semiconductor layer.
11. The semiconductor device of claim 7 , wherein the first sub-semiconductor layer and the second sub-semiconductor layer have the same composition.
12. A display device comprising:
a panel substrate; and
a plurality of semiconductor devices disposed on the panel substrate,
wherein the plurality of semiconductor devices comprises:
a semiconductor structure comprising a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer;
a first electrode electrically connected to the first semiconductor layer; and
a second electrode electrically connected to the second semiconductor layer,
wherein,
the semiconductor structure comprises a first upper surface on which the first semiconductor layer is exposed, a second upper surface on which the second semiconductor layer is disposed, an inclined surface connecting the first upper surface and the second upper surface, and a recess formed between the first upper surface and the inclined surface, and
the recess has a depth less than or equal to 30% of a vertical distance between the first upper surface and the second upper surface, and
wherein a ratio of a first vertical height from a bottom surface of the semiconductor structure to the second upper surface to a second vertical height from the bottom surface of the semiconductor structure to the first upper surface ranges from 1:0.6 to 1:0.95.
13. The display device of claim 12 , wherein,
the second semiconductor layer comprises a first sub-semiconductor layer exposed from the first upper surface and a second sub-semiconductor layer disposed on the first sub-semiconductor layer, and
a difference in etching rate between the first sub-semiconductor layer and the second sub-semiconductor layer is less than or equal to 30% under the same etching conditions.
14. The display device of claim 13 , wherein the first sub-semiconductor layer has a higher etching rate than the second sub-semiconductor layer.
15. The display device of claim 13 , wherein,
the first sub-semiconductor layer contains GaAs, and
the second sub-semiconductor layer contains AlInP.
16. The display device of claim 15 , wherein,
the first sub-semiconductor layer further contains In, and
the first sub-semiconductor layer has a higher In composition than the second sub-semiconductor layer.
17. The display device of claim 13 , wherein the first sub-semiconductor layer and the second sub-semiconductor layer have the same composition.
18. The display device of claim 12 , wherein the first vertical height and the second vertical height have a difference of less than 2 μm.
19. The display device of claim 12 , wherein a first angle between a horizontal surface and the inclined surface is smaller than a second angle between the horizontal surface and a side surface of the semiconductor structure.
20. The display device of claim 12 , wherein the semiconductor structure comprises a long side surface and a short side surface in plane, and
wherein the long side surface is smaller than 100 μm.