Data transfer management within a memory device having multiple memory regions with different memory densities

1. A system comprising:

a memory device comprising a primary region to initially store data received from a host system and one or more secondary regions to store data transferred from the primary region; and

a processing device, operatively coupled with the memory device, the processing device configured to perform operations comprising:

receiving a first portion of a data stream from the host system;

performing a write operation on one or more write units of the primary region with the first portion of the data stream received from the host system, wherein a write unit of the primary region has lower density blocks than a write unit of the secondary region;

monitoring a progress of the write operation to determine whether a subset of write units of the primary region corresponding to a pre-determined number of write units of the primary region is written with the first portion of the data stream received from the host system;

determining that at least one write unit in the subset of write units of the primary region stores invalid data;

in response to determining that the subset of write units of the primary region is written based on the progress of the write operation, performing another write operation on at least one write unit of the secondary region with respective data of the subset of write units of the primary region, the respective data comprising the invalid data; and

receiving a second portion of the data stream from the host system.

2. The system of claim 1 , wherein the operations further comprising:

determining the pre-determined number of write units as a number of write units of the primary region having a total memory density corresponding to a memory density of one or more write units of the secondary region.

3. The system of claim 1 , wherein the operations further comprising:

in response to determining that the subset of write units of the primary region is not fully written based on the progress of the write operation, continuing to write another portion of the data stream from the host system to another one or more write units of the primary region until all write units in the subset of write units of the primary region are written.

4. The system of claim 1 , wherein:

each write unit of the primary region is associated with a single level cell (SLC); and

each write unit of the secondary region is associated with a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).

5. The system of claim 1 , wherein:

each write unit of the primary region is associated with a MLC; and

each write unit of the secondary region is associated with a TLC or a QLC.

6. The system of claim 1 , wherein:

each write unit of the primary region is associated with a TLC; and

each write unit of the secondary region is associated with a QLC.

7. A method comprising:

receiving, at a memory device, a first portion of a data stream from a host system, the memory device comprising a primary region to initially store data received from the host system and one or more secondary regions to store data transferred from the primary region;

performing a write operation on one or more write units of the primary region with the first portion of the data stream received from the host system, wherein a write unit of the primary region has lower density blocks than a write unit of the secondary region;

monitoring a progress of the write operation to determine whether a subset of write units of the primary region corresponding to a pre-determined number of write units of the primary region is written with the first portion of the data stream received from the host system;

determining that at least one write unit in the subset of write units of the primary region stores invalid data;

in response to determining that the subset of write units of the primary region is written based on the progress of the write operation, performing another write operation on at least one write unit of the secondary region with respective data of the subset of write units of the primary region, the respective data comprising the invalid data; and

receiving, at the memory device, a second portion of the data stream from the host system.

8. The method of claim 7 , further comprising:

determining the pre-determined number of write units as a number of write units of the primary region having a total memory density corresponding to a memory density of one or more write units of the secondary region.

9. The method of claim 7 , further comprising:

in response to determining that the subset of write units of the primary region is not fully written based on the progress of the write operation, continuing to write another portion of the data stream from the host system to another one or more write units of the primary region until all write units in the subset of write units of the primary region are written.

10. The method of claim 7 , wherein:

each write unit of the primary region is associated with a single level cell (SLC); and

each write unit of the secondary region is associated with a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).

11. The method of claim 7 , wherein:

each write unit of the primary region is associated with a MLC; and

each write unit of the secondary region is associated with a TLC or a QLC.

12. The method of claim 7 , wherein:

each write unit of the primary region is associated with a TLC; and

each write unit of the secondary region is associated with a QLC.

13. A method comprising:

receiving, at a memory device, a first portion of a data stream from a host system;

writing the first portion of the data stream to one or more write units of a region of the memory device having single-level cell (SLC) blocks; and

determining that four write units of the region of the memory device having SLC blocks are written with the first portion of the data stream received from the host system;

determining that at least one write unit of the four write units in the region of the memory device having SLC blocks stores invalid data;

in response to determining that four write units of the region of the memory device having SLC blocks are written with the first portion of the data stream received from the host system, migrating respective data stored in the four write units of the region of the memory device having SLC blocks to a single write unit of a region of the memory device having quad-level cell (QLC) blocks, the respective data comprising the invalid data; and

receiving, at the memory device, a second portion of the data stream from the host system.

14. The method of claim 13 , further comprising:

receiving a command to delete another portion of the data stream received from the host system, the invalid data corresponding to the another portion of the data stream associated with the command to delete.

15. The method of claim 14 , further comprising:

in response to determining that the at least one write unit of the four write units of the region of the memory device having SLC blocks stores the invalid data, determining a number of write units in the four write units that store the invalid data;

determining one or more write units that correspond to the number of the write units and are not written with the invalid data, wherein the one or more write units are located next to the four write units; and

migrating respective data stored in the one or more write units located next to the four write units and any one or more write units of the four write units that does not store the invalid data to the single write unit of the region of the memory device having QLC blocks.

16. The method of claim 13 , further comprising:

determining whether another four write units of the region of the memory device having SLC blocks that are next to the four write units are written; and

in response to determining that the another four write units of the region of the memory device having SLC blocks are written, migrating respective data stored in the another four write units of the SLC memory region to another write unit of the region of the memory device having QLC blocks that is next to the single write unit of the region of the memory device having QLC blocks.

17. The method of claim 13 , wherein:

the region of the memory device having SLC blocks is smaller than the region of the memory device having QLC blocks;

a write unit of the region of the memory device having SLC blocks corresponds to a page comprising a plurality of SLCs, or a block comprising a plurality of pages; and

a write unit of the region of the memory device having QLC blocks corresponds to a page comprising a plurality of QLCs, or a block comprising the plurality of pages.