Reconfigurable processing-in-memory logic using look-up tables

1. A system, comprising:

a memory array to store a plurality of look-up tables (LUTs) and data;

a control block coupled to the memory array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs; and

a logic array coupled to the memory array and the control block, the logic array to perform, based on control inputs received from the control block, logic operations on the activated LUTs and the data;

wherein the control block controls the logic array and the plurality of LUTs to implement a computational pipeline of systolic arrays.

2. The system of claim 1 , further comprising a cache coupled to the memory array and to the logic array, wherein the cache is utilized to store one or more LUTs of the plurality of LUTs.

3. The system of claim 1 , wherein the logic array comprises at least one of: a full adder, a half adder, a multiplier, or a D-type flip-flop.

4. The system of claim 1 , wherein one or more LUTs of the plurality of LUTs implement one or more logic operations by storing one or more logic operation results in association with a look-up address comprising one or more logic operation inputs.

5. The system of claim 4 , wherein the look-up address identifies a wordline of the memory array.

6. The system of claim 1 , wherein the control block sequentially executes a set of executable instructions stored in the memory array.

7. A system-on-chip (SoC), comprising:

a memory array to store a plurality of look-up tables (LUTs) and data;

one or more logic arrays coupled to the memory array, the one or more logic arrays to:

control a computational pipeline of systolic arrays by activating one or more LUTs of the plurality of LUTs; and

perform logic operations on the activated LUTs and the data.

8. The SoC of claim 7 , further comprising a plurality of sense amplifiers coupled to the memory array.

9. The SoC of claim 7 , further comprising a cache coupled to the memory array and to the one or more logic arrays, wherein the cache is utilized to store one or more LUTs of the plurality of LUTs.

10. The SoC of claim 7 , wherein the one or more logic arrays are further to:

receive executable instructions from the memory array.

11. The SoC of claim 7 , wherein one or more LUTs of the plurality of LUTs implement one or more logic operations by storing one or more logic operation results in association with a look-up address comprising one or more logic operation inputs.

12. A method, comprising:

storing, in a memory array, a plurality of look-up tables (LUTs) and data;

activating, by a control block coupled to the memory array, one or more LUTs of the plurality of LUTs;

performing, by a logic array coupled to the control block and to the memory array, based on control inputs received from the control block, logic operations on the activated LUTs and the data; and

implementing, by the control block controlling the logic array and the plurality of LUTs, a computational pipeline of systolic arrays.

13. The method of claim 12 , further comprising:

storing, in a cache coupled to the memory array and to the logic array, at least one LUT of the plurality of LUTs.

14. The method of claim 12 , wherein the logic array comprises at least one of: a full adder, a half adder, a multiplier, or a D-type flip-flop.

15. The method of claim 12 , wherein one or more LUTs of the plurality of LUTs implement one or more logic operations by storing one or more logic operation results in association with a look-up address comprising one or more logic operation inputs.

16. The method of claim 12 , wherein activating the LUTs is performed responsive to executing an instruction of a set of executable instructions stored in the memory array.