PIM device, computing system including the PIM device, and operating method of the PIM device

1. A processing in memory (PIM) device comprising:

a memory configured to receive data through a first path from a host processor provided outside the PIM device; and

an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path,

wherein the memory is further configured to return the data and the information gatherer is further configured to return the information according to a request of the host processor,

wherein according to a request of the host processor, the memory returns the data to the host processor via a third path, and

wherein the information gatherer returns the information to the host processor through a fourth path that connects the third path to the information gatherer.

2. The PIM device of claim 1 , wherein according to a request of the host processor, the memory returns the data to the host processor through the first path, and

the information gatherer returns the information to the host processor through the second path.

3. The PIM device of claim 1 , further comprising a memory buffer to temporarily store the data transferred from the host processor, wherein

the memory buffer transfers the data to the memory through the first path and transfers the data to the information gatherer through the second path.

4. The PIM device of claim 1 , wherein the information gatherer comprises a processor configured to process the data to generate the information, and at least one register configured to store settings regarding the information, the settings being received from the host processor.

5. The PIM device of claim 4 , wherein the information gatherer comprises at least one of an enabling register to store information whether or not to gather the information from the data, a range register to store a range for gathering the information, a mask register to store a type of information, or an information register file to store the information generated according to the settings.

6. The PIM device of claim 1 , wherein the PIM device is any one of a dynamic random access memory (DRAM), a high band memory (HBM), or a load reduced dual in-line memory module (LRDIMM).

7. A computing system comprising:

a host processor; and

a processing in memory (PIM) device comprising a memory to receive data from the host processor and an information gatherer configured to receive the data and to generate information by processing the data, wherein

the PIM device is configured to transfer the data to the memory via a first path and to transfer the information to the information gatherer via a second path connected to the first path,

the host processor requests any one or any combination of the data and the information from the PIM device,

the PIM device is further configured to return the data from the memory in response to a request for the data, and to return the information from the information gatherer in response to a request for the information,

according to a request of the host processor, the PIM device returns the data to the host processor via a third path, and

the PIM device returns the information to the host processor through a fourth path that connects the third path to the information gatherer.

8. An operating method of a processing in memory (PIM) device, the operating method comprising:

transferring data received from a host processor provided outside the PIM device to a memory through a first path;

transferring the data to an information gatherer via a second path connected to the first path, in response to the data being transferred to the memory via the first path;

generating information by processing the data by the information gatherer; and

returning the data from the memory and returning the information from the information gatherer according to a request of the host processor

wherein the returning of the data from the memory comprises returning the data to the host processor through a third path, and

wherein the returning of the information from the information gatherer comprises returning the information to the host processor through a fourth path that connects the third path to the information gatherer.

9. The operating method of claim 8 , wherein:

the returning of the data from the memory comprises returning the data to the host processor through the first path; and

the returning of the information from the information gatherer comprises returning the information to the host processor through the second path.

10. The operating method of claim 8 , further comprising

temporarily storing the data transferred from the host processor to a memory buffer; and

transferring the data stored at the memory buffer to the memory through the first path and to the information gatherer through the second path.

11. A non-transitory computer-readable recording storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 8 .