Convergence centric coverage for clock domain crossing (CDC) jitter in simulation

1. A method of verifying functionality of a circuit design, the method comprising:

defining one or more design constraints associated with the circuit design;

determining at least one group of converging signals associated with the circuit design using the one or more design constraints;

applying a plurality of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals;

storing, in a jitter database, the plurality of jitters;

determining number of counts that two or more signals in the at least one group of signals toggle jointly;

determining number of jitters associated with each of the counts of the jointly toggling signals; and

determining a test bench coverage from the number of jitters and their associated counts of the jointly toggling signals.

2. The method of claim 1 further comprising:

compiling the circuit design, a test bench associated with the design, and the jitter database; and

applying the test bench and the plurality of jitters to the compiled circuit design using a simulation tool.

3. The method of claim 1 further comprising:

modifying the test bench if the test bench coverage is determined to be less than a threshold value.

4. The method of claim 1 further comprising:

modifying the jitter database if the test bench coverage is determined to be less than a threshold value.

5. The method of claim 1 further comprising:

determining if a first signal in the at least one group of signals toggles singly; and

modifying the test bench or the jitter database to cause the first signal to toggle with at least a second signal of the at least one group of signals.

6. The method of claim 1 further comprising:

determining if a first signal in the at least one group fails to toggle; and

modifying the test bench or the jitter database to cause the first signal to toggle.

7. The method of claim 1 wherein said one or more design constraints define timing relationships between a plurality of clock signals used in the circuit design.

8. A system comprising:

a memory storing instructions; and

a processor coupled with the memory and configured to execute the instructions, the instructions when executed causing the processor to:

define one or more design constraints associated with the circuit design;

determine at least one group of converging signals associated with the circuit design;

apply a plurality of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals;

store, in a jitter database, the plurality of jitters;

determine number of counts that two or more signals in the at least one group of signals toggle jointly;

determine number of jitters associated with each of the counts of the jointly toggling signals; and

determine a test bench coverage from the number of jitters and their associated counts of the jointly toggling signals.

9. The system of claim 8 wherein said instructions further cause the processor to:

compile the circuit design, a test bench associated with the design, and the jitter database; and

apply the test bench and the plurality of jitters to the compiled circuit design using a simulation tool.

10. The system of claim 8 wherein said instructions further cause the processor to:

modify the test bench or the jitter database if the coverage is determined to be less than a threshold value.

11. The system of claim 8 wherein said instructions further cause the processor to:

determine if a first signal in the at least one group of signals toggles singly; and

modify the test bench or the jitter database to cause the first signal to toggle with at least a second signal of the at least one group of signals.

12. The system of claim 8 wherein said instructions further cause the processor to:

determine if a first signal in the at least one group fails to toggle; and

modify the test bench or the jitter database to cause the first signal to toggle.

13. The system of claim 8 wherein said one or more design constraints define timing relationships between a plurality of clock signals used in the circuit design.

14. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

define one or more design constraints associated with the circuit design;

determine at least one group of converging signals associated with the circuit design;

apply a plurality of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals;

store, in a jitter database, the plurality of jitters;

determine number of counts that two or more signals in the at least one group of signals toggle jointly;

determine number of jitters associated with each of the counts of the jointly toggling signals; and

determine a test bench coverage from the number of jitters and their associated counts of the jointly toggling signals.

15. The non-transitory computer readable medium of claim 14 wherein said instructions further cause the processor to:

compile the circuit design, a test bench associated with the design, and the jitter database; and

apply the test bench and the plurality of jitters to the compiled circuit design using a simulation tool.

16. The non-transitory computer readable medium of claim 14 wherein said instructions further cause the processor to:

modify the test bench if the coverage is determined to be less than a threshold value.

17. The non-transitory computer readable medium of claim 14 wherein said instructions further cause the processor to:

modify the jitter database if the coverage is determined to be less than a threshold value.

18. The non-transitory computer readable medium of claim 14 wherein said instructions further cause the processor to:

determine if a first signal in the at least one group of signals toggles singly; and

modify the test bench or the jitter database to cause the first signal to toggle with at least a second signal of the at least one group of signals.

19. The non-transitory computer readable medium of claim 14 wherein said instructions further cause the processor to:

determine if a first signal in the at least one group fails to toggle; and

modify the testbench or the jitter database to cause the first signal to toggle.

20. The non-transitory computer readable medium of claim 14 wherein said one or more design constraints define timing relationships between a plurality of clock signals used in the circuit design.