Vertically stacked finFETs and shared gate patterning
Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.
1. A transistor structure, comprising:
a fin including a first layer of semiconductor material under or over a second layer of semiconductor material;
a first gate stack adjacent to one or more sidewalls of the fin and adjacent to the first layer of semiconductor material, wherein the first gate stack includes a first gate electrode and a first gate dielectric layer;
a first source terminal and a first drain terminal coupled to the first layer of semiconductor material and on opposite sides of the first gate stack, wherein the first source and drain terminals comprise N-type semiconductor;
a second gate stack adjacent to one or more sidewalls of the fin and adjacent to the second layer of semiconductor material, wherein the second gate stack includes a second gate electrode and a second gate dielectric layer;
a second source terminal and a second drain terminal coupled to the second layer of semiconductor material and on opposite sides of the second gate stack, wherein the second source and drain terminals comprise P-type semiconductor;
a subfin comprising one or more crystalline materials between the first and second layers of semiconductor material; and
an isolation dielectric adjacent to one or more sidewalls of the subfin, the isolation dielectric between the first gate stack and the second gate stack.
2. The transistor structure of claim 1 , wherein a centerline of the first gate electrode is in vertical alignment with a centerline of the second gate electrode.
3. The transistor structure of claim 1 , wherein:
a first channel height is equal to a height of the fin adjacent to the first gate stack;
a second channel height is equal to a height of the fin adjacent to the second gate stack;
the subfin has a subfin height equal to a vertical spacing between the first and second gate stacks; and
the fin has a total height equal to the first channel height summed with the second channel height and the subfin height therebetween.
4. The transistor structure of claim 1 , wherein the isolation dielectric further comprises:
a first layer of dielectric material adjacent to a subfin portion of the fin and between the first and second gate electrodes; and
a second layer of dielectric material that is adjacent to the first layer of dielectric material.
5. The transistor structure of claim 4 , wherein the fin is a first fin, and the structure further comprises:
a second fin including the first layer of semiconductor material and the second layer of semiconductor material;
a third gate stack adjacent to one or more sidewalls of the second fin and adjacent to the first layer of semiconductor material;
a fourth gate stack adjacent to one or more sidewalls of the second fin and adjacent to the second layer of semiconductor material; and wherein:
the first layer of dielectric material is adjacent to a subfin portion of the second fin located between the third and fourth gate stacks;
the second layer of dielectric material separates the first gate stack from the third gate stack, and separates the second gate stack from the fourth gate stack; and
the second layer of dielectric material separates the first layer of dielectric material adjacent to the second fin from the first layer of dielectric material adjacent to the first fin.
6. The transistor structure of claim 4 , wherein:
the first layer of dielectric material is adjacent to a subfin portion of the first layer of semiconductor material;
the structure further comprises a third layer of dielectric material adjacent to a subfin portion of the second layer of semiconductor material; and
the second layer of dielectric material is adjacent to both the first and the third layers of dielectric material.
7. The transistor structure of claim 6 , wherein the first layer of dielectric material has fixed charge of a first polarity and the third layer of dielectric material has fixed charge of a second polarity, complementary to the first polarity.
8. The transistor structure of claim 7 , wherein the first layer of dielectric material has negative fixed charge and the third layer of dielectric material has positive fixed charge.
9. The transistor structure of claim 7 , wherein the first layer of dielectric material has a concentration of fixed charges of at least 10 12 per square centimeter, and the third layer of dielectric material has a concentration of fixed charges of at least 10 12 per square centimeter.
10. The transistor structure of claim 7 , wherein the second layer of dielectric material comprises phosphorus-doped silicate glass (PSG).
11. The transistor structure of claim 6 , wherein the first layer of dielectric material comprises one or more acceptor impurities that are also present in the subfin portion of the first layer of semiconductor material, and wherein the second layer of dielectric material comprises one or more donor impurities that are also present in the subfin portion of the second layer of semiconductor material.
12. The transistor structure of claim 6 , further comprising a barrier layer located between the first and second layers of dielectric material.
13. The transistor structure of claim 4 , wherein the first layer of dielectric material has fixed charge of a first polarity.
14. The transistor structure of claim 13 , wherein the first layer of dielectric material has a concentration of fixed charges of at least 10 12 per square centimeter.
15. The transistor structure of claim 1 , wherein:
the first layer of semiconductor material comprises a Group III-V semiconductor; and
the second layer of semiconductor material comprises a Group IV semiconductor.
16. A system comprising:
an electronic memory; and
a processor coupled to the memory, the processor comprising a CMOS circuit including a plurality of NMOS and PMOS field effect transistors (FETs), wherein a first of the NMOS and PMOS FETs further comprise the transistor structure of claim 1 .
17. The system of claim 16 , further comprising:
a wireless communication antenna coupled to the processor; and
a battery coupled to at least one of the processor and memory.
18. The transistor structure of claim 1 , wherein the one or more crystalline materials are in direct contact with the first and second semiconductor material layers.
19. The transistor structure of claim 1 , wherein the one or more crystalline materials and the first and second semiconductor material layers are substantially monocrystalline.
20. The transistor structure of claim 1 , wherein the subfin comprises a first crystalline material layer in contact with a second crystalline material layer, the first and second crystalline material layers comprising a pseudomorphic or metamorphic heterostructure.