IP Library › Granted Patent US 11,404,390
Granted Patent B2
US 11,404,390 · App. 16/916,325 · Granted Aug 2, 2022

Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars

Inventor: Chao Wen Wang (Taichung, TW)
Assignee: Micron Technology, Inc.
H01L24/11H01L24/13H01L2224/11011H01L2224/1146H01L2224/1147H01L2224/11912
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Quick Facts
Patent No.
US 11,404,390
App. No.
16/916,325
Granted
Aug 2, 2022
Kind
B2
Abstract

Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Claims (17)

1. A method comprising:

forming a sacrificial layer over a region of a semiconductor device;

forming one or more first pillars over the sacrificial layer, and one or more second conductive pillars over corresponding bond pads that are not covered by the sacrificial layer; and

detaching the one or more first pillars from the semiconductor device by removing the sacrificial layer over which the one or more first pillars are formed.

2. The method of claim 1 , further comprising:

determining a lateral dimension of the region that includes a first areal density of the one or more first pillars based on a second areal density of the one or more second conductive pillars.

3. The method of claim 2 , wherein the first areal density correlates to the second areal density such that heights of the one or more second conductive pillars are within a predetermined range.

4. The method of claim 2 , wherein the first areal density is approximately same as the second areal density.

5. The method of claim 1 , further comprising:

forming a seed layer over the semiconductor device, wherein the sacrificial layer is formed on the seed layer in the region, and the seed layer covers the bond pads.

6. The method of claim 1 , wherein:

forming the one or more first pillars over the sacrificial layer includes attaching the one or more first pillars to the sacrificial layer; and

forming the one or more second conductive pillars over the corresponding bond pads includes attaching the one or more second conductive pillars to a seed layer that is formed on the bond pads.

7. The method of claim 1 , further comprising:

removing the sacrificial layer from the region of the semiconductor device, wherein the one or more first pillars protect the sacrificial layer over which the one of more first pillars are formed.

8. The method of claim 7 , wherein removing the sacrificial layer includes a blanket dry etch process having a selectivity against a seed layer.

9. The method of claim 1 , wherein the one or more sacrificial pillars are formed concurrently with the one or more second conductive pillars.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2020
From: WANG, CHAO WEN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 053084/0768 →
Continuity (1)
Related Publication 20210407944A1 · Dec 30, 2021