Memory device comprising an electrically floating body transistor

1. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region on opposite sides of said floating body region; and

a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region, wherein:

said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said semiconductor memory cell;

wherein said well region bounds at least two sides of said floating body region.

2. The semiconductor memory cell of claim 1 , wherein said application of said back bias results in at least two stable floating body charge levels.

3. The semiconductor memory cell of claim 1 , wherein said semiconductor memory cell comprises a fin structure.

4. The semiconductor memory cell of claim 1 , wherein said semiconductor memory cell comprises a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions, wherein:

said depletion region is formed as a result of an application of said back bias to said buried layer region.

5. The semiconductor memory cell of claim 1 , wherein said depletion region is formed as a result of an application of said back bias to said well region.

6. The semiconductor memory cell of claim 4 , further comprising an access transistor;

wherein said access transistor comprises said well region, and

wherein said well region of said access transistor is electrically connected to said buried layer region.

7. The semiconductor memory cell of claim 1 , wherein said well region comprises well regions adjacent to said floating body region on opposite sides of said floating body region.

8. The semiconductor memory cell of claim 4 , wherein said well region comprises well regions adjacent to said floating body region on opposite sides of said floating body region; and

wherein said well regions are electrically connected to said buried layer region.

9. A method of operating a semiconductor memory cell comprising:

providing a memory cell comprising a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a first insulating region located above said floating body region; second insulating regions adjacent to said floating body region on opposite sides of said floating body region; a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region; and

forming a depletion region by applying a back bias to said memory cell so that said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and said depletion region;

wherein said memory cell comprises an access transistor;

wherein said access transistor comprises said well region; and

wherein said well region of said access transistor is electrically connected to said buried layer region.

10. The method of claim 9 , wherein said applying said back bias results in at least two stable floating body charge levels.

11. The method of claim 9 , wherein said semiconductor memory cell comprises a fin structure.

12. The method of claim 11 , wherein said applying said back bias comprises applying said back bias to said well region, and wherein said applying said back bias to said buried layer region occurs through said applying said back bias to said well region.

13. The method of claim 11 , wherein said well region comprises well regions adjacent to said floating body region on opposite sides of said floating body region.

14. The method of claim 9 , wherein said well region comprises well regions adjacent to said floating body region on opposite sides of said floating body region; and

wherein said well regions are electrically connected to said buried layer region.

15. The method of claim 9 , wherein said applying said back bias comprises applying said back bias to a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions.

16. A semiconductor memory cell comprising:

a bi-stable floating body transistor comprising a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states;

an access device; and

a non-volatile memory comprising a resistance change element;

wherein said bi-stable floating body transistor and said access device are electrically connected in series; and

wherein said bi-stable floating body transistor and said non-volatile memory element are electrically connected in series.

17. The semiconductor memory cell of claim 16 , wherein said non-volatile memory is configured to store data upon transfer from said bi-stable floating body transistor.

18. The semiconductor memory cell of claim 16 , wherein said non-volatile memory is configured to restore data to said floating body transistor.

19. The semiconductor memory cell of claim 18 , wherein said non-volatile memory is reset to an initial state after restoring data to said floating body transistor.

20. A semiconductor memory cell comprising:

a bi-stable floating body transistor comprising a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states;

an access device; and

a non-volatile memory comprising a resistance change element;

wherein said bi-stable floating body transistor stores data when power is applied to said memory cell; and

wherein said non-volatile memory stores data when power is discontinued from said memory cell.

21. The semiconductor memory cell of claim 20 , wherein said non-volatile memory is configured to store data upon transfer from said floating body transistor.

22. The semiconductor memory cell of claim 20 , wherein said non-volatile memory is configured to restore data to said floating body transistor.

23. The semiconductor memory cell of claim 22 , wherein said non-volatile memory is reset to an initial state after restoring data to said floating body transistor.

24. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions;

a first insulating region located above said floating body region;

second insulating regions adjacent to said floating body region on opposite sides of said floating body region; and

a well region adjacent to said floating body region and having a different conductivity type from a conductivity type of said floating body region;

an access transistor, wherein said access transistor comprises said well region; and

a buried layer region located below said floating body region and said second insulating regions and spaced from said second insulating regions so as not to contact said second insulating regions;

wherein said floating body region is bounded by said first insulating region above said floating body region, said second insulating regions adjacent to said floating body region, said well region, and a depletion region formed as a result of an application of a back bias to said semiconductor memory cell;

wherein said well region of said access transistor is electrically connected to said buried layer region; and

wherein said depletion region is formed as a result of an application of said back bias to said buried layer region.