IP Library › Granted Patent US 11,404,566
Granted Patent B2
US 11,404,566 · App. 16/984,136 · Granted Aug 2, 2022

Semiconductor device

Inventor: Yasuyuki Hoshi (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/7811H01L29/0696H01L29/0865H01L29/0869H01L29/41741H01L29/66068H01L29/7813H01L29/1608
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Quick Facts
Patent No.
US 11,404,566
App. No.
16/984,136
Granted
Aug 2, 2022
Kind
B2
Abstract

A semiconductor device includes an active region, a gate ring region surrounding a periphery of the active region, and a source ring region surrounding a periphery of the gate ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and a second electrode. The semiconductor device has, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film and a first first-electrode, and has, in the source ring region, a third semiconductor region and a second first-electrode. In the source ring region, a second semiconductor region of the first or second conductivity type is provided at a bottom of the third semiconductor region, directly below the second first-electrode in a depth direction of the semiconductor device.

Claims (37)

1. A semiconductor device having

an active region through which a main current flows,

a gate ring region surrounding a periphery of the active region,

a ring region surrounding a periphery of the gate ring region, and

a termination region surrounding a periphery of the ring region, the semiconductor device comprising:

a semiconductor substrate of a first conductivity type, the semiconductor substrate having a front surface and a back surface opposite to each other;

a first semiconductor layer of the first conductivity type, provided at the front surface of the semiconductor substrate and having an impurity concentration lower than an impurity concentration of the semiconductor substrate, the first semiconductor layer having a first side and a second side opposite to each other, the second side facing the semiconductor substrate;

a second semiconductor layer of a second conductivity type, provided at a surface of the first semiconductor layer at the first side thereof, the second semiconductor layer having a first side and a second side opposite to each other, the second side of the second semiconductor layer facing the semiconductor substrate;

in the active region:

a plurality of first semiconductor regions of the first conductivity type, selectively provided in a surface layer of the second semiconductor layer at the first side thereof,

a gate insulating film having a first side and a second side opposite to each other, a surface of the gate insulating film at the second side thereof being in contact with the second semiconductor layer,

a plurality of first gate electrodes provided at a surface of the gate insulating film at the first side thereof,

an interlayer insulating film provided on the plurality of first gate electrodes,

a first first-electrode provided at a surface of the second semiconductor layer and surfaces of the plurality of first semiconductor regions;

in the ring region:

a second first-electrode provided at the surface of the second semiconductor layer, and

a third semiconductor region of the second conductivity type, provided at the surface of the first semiconductor layer so as to be in contact with the second semiconductor layer, the third semiconductor region having an impurity concentration higher than an impurity concentration of the second semiconductor layer, and

a second semiconductor region, of the first conductivity type or of the second conductivity type, provided at a bottom of the third semiconductor region, directly below the second first-electrode in a depth direction of the semiconductor device; and

a second electrode provided at the back surface of the semiconductor substrate.

2. The semiconductor device according to claim 1 , further comprising, in the ring region, a second trench that penetrates one of the plurality of first semiconductor regions, penetrates the second semiconductor layer, and reaches the third semiconductor region, wherein

the second first-electrode is provided in the second trench.

3. The semiconductor device according to claim 1 , wherein

the second semiconductor region has a quadrilateral shape in a plan view of the semiconductor device, each side of the quadrilateral shape having protruding and concave parts.

4. The semiconductor device according to claim 1 , further comprising,

in the active region,

a plurality of first trenches penetrating the plurality of first semiconductor regions and the second semiconductor layer, and reaching the first semiconductor layer,

a plurality of fourth semiconductor regions of the second conductivity type, selectively provided in the first semiconductor layer, directly below bottoms of the plurality of first trenches respectively in the depth direction of the semiconductor device, and

a plurality of the third semiconductor region, each provided between adjacent two of the plurality of first trenches, wherein

the plurality of first gate electrodes are respectively provided in the plurality of first trenches, via the gate insulating film.

5. The semiconductor device according to claim 4 , wherein

a bottom of the second semiconductor region is deeper than bottoms of the plurality of fourth semiconductor regions in the depth direction of the semiconductor device.

6. The semiconductor device according to claim 1 , further comprising, in the ring region, a plating film selectively provided on the second first-electrode.

7. The semiconductor device according to claim 1 , further comprising, in the gate ring region,

the third semiconductor region,

a first insulating film having a first side and a second side opposite each other, a surface of the first insulating film at the second side thereof being in contact with the second semiconductor layer,

a second gate electrode provided at a surface of the first insulating film at the first side thereof, and

a gate wiring electrode provided on the second gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2020
From: HOSHI, YASUYUKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 053388/0613 →
Priority Claims (1)
JP JP2019-162543 · Sep 6, 2019 · national
Continuity (1)
Related Publication 20210074846A1 · Mar 11, 2021