Solid-state imaging device

1. A solid-state imaging device, comprising:

a first substrate that includes:

a principal surface;

a first semiconductor substrate; and

a first multi-layer wiring layer that includes:

a first surface in contact with the first semiconductor substrate; and

a second surface opposite to the first surface and the principal surface;

a pixel portion on the principal surface, wherein the pixel portion includes a plurality of pixels;

a second substrate that includes:

a second semiconductor substrate;

a second multi-layer wiring layer that includes:

a third surface in contact with the second semiconductor substrate; and

a fourth surface in contact with the second surface of the first multi-layer wiring layer;

a specific surface opposite to the fourth surface of the second multi-layer wiring layer; and

an opening in a partial region of the second substrate, wherein the opening is on the specific surface of the second substrate; and

at least one sub-chip inside the opening, wherein the at least one sub-chip includes a first circuit configured to execute a first function.

2. The solid-state imaging device according to claim 1 , wherein

the second substrate further includes a first electrode,

the at least one sub-chip includes a second electrode in contact with the first electrode of the second substrate, and

the second substrate is electrically connectable to the at least one sub-chip via the first electrode and the second electrode.

3. The solid-state imaging device according to claim 1 , wherein

the second substrate further includes a plurality of substrates,

the plurality of substrates includes the second semiconductor substrate, and

the second semiconductor substrate includes a through hole corresponding to the opening.

4. The solid-state imaging device according to claim 3 , wherein each of the first substrate and the second substrate includes second circuit configured to execute a second function.

5. The solid-state imaging device according to claim 4 , wherein the first circuit of the at least one sub-chip includes a memory circuit.

6. The solid-state imaging device according to claim 4 , wherein the second circuit of the second substrate includes at least one of a logic circuit or an analog-digital conversion circuit.

7. The solid-state imaging device according to claim 5 , wherein each of the first substrate and the second substrate includes the same material.

8. The solid-state imaging device according to claim 1 , wherein

the at least one sub-chip has a surface height on a side of the opening substantially same as a surface height of an opening surface of the opening.

9. The solid-state imaging device according to claim 1 , wherein

the at least one sub-chip further includes a third semiconductor substrate and a third multi-layer wiring layer, and

the third semiconductor substrate includes a material different from a material of each of the first semiconductor substrate and the second semiconductor substrate.

10. The solid-state imaging device according to claim 1 , further comprising a third multi-layer wiring layer on the second substrate, wherein

the third multi-layer wiring layer covers the opening, and

the third multi-layer wiring layer is configured to electrically connect the at least one sub-chip and the second substrate.

11. The solid-state imaging device according to claim 10 , wherein

the at least one sub-chip further includes:

a third semiconductor substrate and a fourth multi-layer wiring layer; and

a sub-chip through electrode that passes through the third semiconductor substrate,

the second substrate further includes a second substrate through electrode, and

the third multi-layer wiring layer is configured to electrically connect the at least one sub-chip and the second substrate via the the second substrate through electrode and the sub-chip through electrode.

12. The solid-state imaging device according to claim 11 , further comprising a third substrate on the third multi-layer wiring layer, wherein the third substrate includes a second circuit configured to execute second function.

13. The solid-state imaging device according to claim 12 , wherein

the second substrate includes an analog-digital conversion circuit, and

the third substrate includes a logic circuit.

14. The solid-state imaging device according to claim 1 , further comprising:

a second substrate through electrode that passes through the second semiconductor substrate; and

a third multi-layer wiring layer on the second substrate, wherein

the third multi-layer wiring layer covers the opening,

the third multi-layer wiring layer includes an external input/output terminal, and

the external input/output terminal is electrically connectable to the second substrate through electrode.

15. The solid-state imaging device according to claim 14 , wherein the external input/output terminal overlaps one of the second substrate or the at least one sub-chip.

16. The solid-state imaging device according to claim 14 , wherein the external input/output terminal is a solder ball.

17. The solid-state imaging device according to claim 1 , further comprising a plurality of sub-chips inside the opening, wherein the plurality of sub-chips includes the at least one sub-chip.

18. The solid-state imaging device according to claim 1 , wherein the second substrate further includes one of an alignment mark or a monitor mark in the specific surface of the second substrate.

19. The solid-state imaging device according to claim 18 , wherein the one of the alignment mark or the monitor mark is a slit pattern having a depth substantially same depth as a of the opening.

20. A solid-state imaging device, comprising:

a first substrate that includes:

a first surface;

a principal surface opposite to the first surface; and

a pixel portion on the principal surface, wherein the pixel portion includes a plurality of pixels;

a second substrate that includes:

a second surface in contact with the first surface of the first substrate;

a third surface opposite to the second surface;

a semiconductor substrate;

a first multi-layer wiring layer; and

an opening in a partial region in the third surface;

a through electrode that passes through the semiconductor substrate;

a second multi-layer wiring layer on the second substrate, wherein

the second multi-layer wiring layer covers the opening,

the second multi-layer wiring layer includes an external input/output terminal, and

the external input/output terminal is electrically connectable to the through electrode; and

at least one sub-chip inside the opening, wherein the at least one sub-chip includes a circuit configured to execute a specific function.