Persisting configuration information
A method for non-disruptive upgrade of a storage system is provided. The method includes disabling, by an interlock, access by one or more processors of the storage system to the first memory, responsive to a request. The method includes persisting configuration information in the first memory to the solid-state memory, with the access to the first memory disabled by the interlock, wherein the persisting, the first memory and the solid-state memory are supported by an energy reserve. The method includes enabling, by the interlock, access by the one or more processors to the first memory, responsive to completing the persisting, and writing, by the one or more processors of the storage system, to the first memory, to perform the upgrade with further configuration information, with the access enabled by the interlock and wherein at least the persisting is accomplished without power cycling.
1. A method, comprising:
disabling access by one or more processors of a plurality of storage nodes of the storage system to a first memory of a storage unit of the storage system through an interlock, wherein each of the plurality of storage nodes generate error correction coded data stripes and write the data stripes across the plurality of storage nodes;
persisting configuration information for a controller of the storage unit in the first memory to a second memory in the storage unit, the second memory including solid state memory; and
modifying, by the one or more processors of the storage system, the configuration information in the first memory to provide further configuration information, with access enabled by the interlock and responsive to completing the persisting, wherein the controller is configured to provide the interlock in the storage unit that disables and enables access by the one or more processors of the plurality of storage nodes to the first memory in the storage unit, the configuration information specifies a format of data layout in a RAM (random access memory), each of the plurality of storage nodes configurable to perform an upgrade to the storage system by writing further configuration information to the first memory.
2. The method of claim 1 , further comprising:
detecting the disabling by accessing one or more bits of one or more registers.
3. The method of claim 1 , wherein the persisted configuration information represents a first state and the further configuration information modifies a data layout applied to data associated with the first state.
4. The method of claim 1 , wherein the method is achieved without power cycling the storage system.
5. The method of claim 1 , wherein the persisting is supported by an energy reserve.
6. The method of claim 1 , wherein the storage system comprises a plurality of storage nodes organized as a storage cluster, with the one or more processors of the storage system being in the storage nodes and the persisting occurring in a storage unit having the first memory, the second memory and an energy reserve.
7. The method of claim 1 , wherein:
the persisting comprises writing contents of a RAM (random access memory) as the first memory to the second memory during a power interruption.
8. A storage system, comprising:
a first memory in each of a plurality of storage units of the storage system, configurable to contain configuration information;
a solid-state memory in each of the plurality of storage units of the storage system, configurable for storage of data;
one or more processors in each of a plurality of storage nodes of the storage system, coupled to the plurality of storage units of the storage system and configurable to perform I/O (input/output) operations for the storage system, with each of the plurality of storage nodes configurable to generate error correction coded data stripes and write the data stripes across the plurality of storage nodes;
a controller in each of the plurality of storage units of the storage system, coupled to the first memory and the solid-state memory, the controller configurable to provide an interlock in the storage unit that disables and enables access by the one or more processors of the plurality of storage nodes to the first memory in the storage unit; and
the controller further configurable to persist configuration information in the first memory to the solid-state memory in the storage unit, responsive to the interlock disabling the access by the one or more processors to the first memory, wherein the configuration information specifies a format of data layout in a RAM (random access memory) each of the plurality of storage nodes configurable to perform an upgrade to the storage system by writing further configuration information to the first memory.
9. The storage system of claim 8 , further comprising:
the controller having one or more bits to which the one or more processors have write access to request that the controller persists the configuration information, as a portion of the interlock.
10. The storage system of claim 8 , wherein:
the configuration information and the further configuration information specify a configuration of a PLD (programmable logic device).
11. The storage system of claim 8 , wherein:
the controller comprises a PLD (programmable logic device).
12. The storage system of claim 8 , further comprising:
a plurality of storage nodes as a storage cluster, each of the plurality of storage nodes having one or more storage units, the plurality of storage nodes having the one or more processors, the plurality of storage units having the one or more further processors, the first memory and the solid-state memory.
13. The storage system of claim 8 , further comprising:
the controller configured to perform the upgrade as a non-disruptive upgrade without power cycling.
14. A tangible, non-transitory, computer-readable media having instructions thereupon which, when executed by a processor in a storage system, cause the processor to perform a method comprising:
disabling access by one or more processors of a plurality of storage nodes of the storage system to a first memory of a storage unit of the storage system through an interlock, wherein each of the plurality of storage nodes generate error correction coded data stripes and write the data stripes across the plurality of storage nodes;
detecting the disabling;
persisting configuration information for a controller of the storage unit in the first memory to a second memory in the storage unit, the second memory including solid state memory; and
modifying, by the one or more processors of the storage system, the configuration information in the first memory to provide further configuration information, with access enabled by the interlock and responsive to completing the persisting, wherein the controller is configured to provide the interlock in the storage unit that disables and enables access by the one or more processors of the plurality of storage nodes to the first memory in the storage unit, the configuration information specifies a format of data layout in a RAM (random access memory) each of the plurality of storage nodes configurable to perform an upgrade to the storage system by writing further configuration information to the first memory.
15. The computer-readable media of claim 14 , wherein detecting the disabling includes accessing one or more bits of one or more registers.
16. The computer-readable media of claim 14 , wherein the persisted configuration information represents a first state and the further configuration information modifies a data layout applied to data associated with the first state.
17. The computer-readable media of claim 14 , wherein the method is achieved without power cycling the storage system.
18. The computer-readable media of claim 14 , wherein the persisting is supported by an energy reserve.
19. The computer-readable media of claim 14 , wherein the storage system comprises a plurality of storage nodes organized as a storage cluster, with the one or more processors of the storage system being in the storage nodes and the persisting occurring in a storage unit having the first memory, the solid-state memory and an energy reserve.