Semiconductor memory device and manufacturing method of the semiconductor memory device

1. A semiconductor memory device, comprising:

a channel structure including a memory layer storing data;

a contact pattern comprising a vertical contact part, and a sidewall contact part extending from the vertical contact part in a direction crossing the vertical contact part, wherein the sidewall contact part is coupled to the vertical contact part, and wherein the contact pattern is disposed apart from the channel structure;

a lower conductive pattern having a hole into which the vertical contact part is inserted; and

an upper conductive pattern overlapping a portion of the lower conductive pattern,

wherein the upper conductive pattern comprises a first side portion in contact with the sidewall contact part, and a second side portion facing the vertical contact part and spaced apart from the vertical contact part.

2. The semiconductor memory device according to claim 1 ,

wherein the second side portion is curved, and

wherein the first side portion is flat.

3. The semiconductor memory device according to claim 1 , wherein an edge of the hole is spaced apart from the vertical contact part.

4. The semiconductor memory device according to claim 1 , wherein the lower conductive pattern comprises:

a first overlap area overlapping the upper conductive pattern;

a second overlap area extending from the first overlap area to overlap the sidewall contact part; and

an extension area extending from the second overlap area, and

wherein the second overlap area is disposed between the first overlap area and the extension area.

5. The semiconductor memory device according to claim 4 , wherein the hole passes through the second overlap area, and extends into the first overlap area and the extension area.

6. The semiconductor memory device according to claim 4 , wherein the vertical contact part include a first protrusion protruding towards the second side portion of the upper conductive pattern and a second protrusion protruding towards the extension area of the lower conductive pattern.

7. The semiconductor memory device according to claim 1 , wherein the sidewall contact part includes a protrusion that farther protrudes upwards than the upper conductive pattern.

8. The semiconductor memory device according to claim 1 , wherein the contact pattern is electrically coupled to the upper conductive pattern and is electrically isolated from the lower conductive pattern because of a gap located between the lower conductive pattern and the vertical contact part.

9. A semiconductor memory device, comprising:

a gate stack having conductive patterns that are stacked while being spaced apart from each other in a stacking direction, and form a stepped structure;

channel structures including memory cells in the gate stack;

sidewall contact parts formed on sidewalls of the conductive patterns, respectively;

vertical contact parts extending in the stacking direction from the sidewall contact parts, respectively, wherein the vertical contact parts are coupled to the sidewall contact parts, respectively, and the vertical contact parts are disposed apart from the channel structures; and

spacer insulating layers disposed between the vertical contact parts and the conductive patterns.

10. The semiconductor memory device according to claim 9 , wherein the vertical contact parts extend parallel to each other.

11. The semiconductor memory device according to claim 9 , further comprising:

a substrate disposed under the gate stack and comprising a peripheral circuit;

interconnection structures coupled to the peripheral circuit, between the substrate and the gate stack;

a doped semiconductor layer disposed between the interconnection structures and the gate stack; and

insulating layers passing through the doped semiconductor layer,

wherein the vertical contact parts pass through the insulating layers, respectively, and extend to come into contact with the interconnection structures, respectively.

12. The semiconductor memory device according to claim 11 , further comprising:

a dummy stepped structure comprising dummy interlayer insulating layers and dummy conductive patterns that are alternately stacked on the doped semiconductor layer;

a support pillar passing through the dummy stepped structure; and

a dummy spacer insulating layer formed on a surface of the support pillar.

13. The semiconductor memory device according to claim 12 , further comprising:

pad sacrificial layers formed on sidewalls of the dummy conductive patterns, respectively; and

a dummy blocking insulating layer extending along an interface between each of the dummy conductive patterns and a corresponding pad sacrificial layer, interfaces between the respective dummy conductive patterns and corresponding dummy interlayer insulating layers, and an interface between each of the dummy conductive patterns and the dummy spacer insulating layer.

14. The semiconductor memory device according to claim 13 , wherein the dummy conductive patterns extend from the conductive patterns, respectively, and

the pad sacrificial layers come into contact with sidewalls of the sidewall contact parts, respectively.

15. The semiconductor memory device according to claim 13 , wherein the dummy spacer insulating layer extends between the dummy interlayer insulating layers that are adjacent in the stacking direction.

16. The semiconductor memory device according to claim 13 , wherein each of the pad sacrificial layers comprises a material having higher etching resistance to phosphoric acid than a nitride layer.

17. The semiconductor memory device according to claim 9 , further comprising:

a dummy buffer stack comprising dummy interlayer insulating layers and horizontal sacrificial layers that are alternately stacked in the stacking direction;

a contact plug passing through the dummy buffer stack; and

dummy spacer insulating layers disposed between the horizontal sacrificial layers and the contact plug.

18. The semiconductor memory device according to claim 9 , wherein the gate stack further comprises interlayer insulating layers that are stacked while being spaced apart from each other in the stacking direction,

wherein each of the conductive patterns is disposed between a pair of upper interlayer insulating layer and lower interlayer insulating layer that are adjacent to each other in the stacking direction, among the interlayer insulating layers.

19. The semiconductor memory device according to claim 18 , wherein each of the sidewall contact parts is disposed between an end of the upper interlayer insulating layer and the lower interlayer insulating layer.

20. The semiconductor memory device according to claim 18 , wherein the spacer insulating layers are disposed between the interlayer insulating layers.

21. The semiconductor memory device according to claim 9 , further comprising:

a blocking insulating layer extending along a surface of each of the conductive patterns,

wherein the blocking insulating layer is penetrated by a corresponding sidewall contact part among the sidewall contact parts.