IP Library › Granted Patent US 11,410,978
Granted Patent B2
US 11,410,978 · App. 16/762,090 · Granted Aug 9, 2022

Process for fabrication of an optoelectronic device comprising a plurality of diodes

Inventors: Hubert Bono (Grenoble, FR); Julia Simon (Grenoble, FR)
Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives; Thales
H01L25/167H01L33/0095H01L33/44H01L33/62H01L27/156H01L2933/0066
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Quick Facts
Patent No.
US 11,410,978
App. No.
16/762,090
Granted
Aug 9, 2022
Kind
B2
Abstract

A method of manufacturing an optoelectronic device, including: a) transferring, onto a surface of a control circuit, a diode stack including first and second semiconductor layers of opposite conductivity types, so that the second layer is electrically connected to metal pads of the control circuit; b) forming in the active stack trenches delimiting a plurality of diodes connected to separate metal pads of the control circuit; c) depositing an insulating layer on the lateral walls of the trenches; d) partially removing the insulating layer to expose the sides of the portions of the first layer delimited by the trenches; and e) forming a metallization coating the lateral walls and the bottom of the trenches and contacting the sides of the portions of the first layer delimited by the trenches.

Claims (20)

1. A method of manufacturing an optoelectronic device, comprising the steps of:

a) transferring, onto a surface of an integrated control circuit comprising a plurality of metal connection pads, an active diode stack comprising at least first and second doped semiconductor layers of opposite conductivity types, so that the second layer of the stack is electrically connected to the metal pads of the control circuit;

b) forming in the active stack trenches delimiting a plurality of diodes connected to separate metal pads of the control circuit;

c) depositing an insulating layer on the lateral walls of the trenches;

d) partially removing the insulating layer to expose the sides of the portions of the first semiconductor layer delimited by the trenches; and

e) forming a metallization coating the lateral walls and the bottom of the trenches and contacting the sides of the portions of the first semiconductor layer delimited by the trenches;

before step a), at least one of the following steps:

a step of depositing at least one first metal layer over substantially the entire surface of the control circuit on the side of the metal pads; and

a step of depositing at least one second metal layer over substantially the entire surface of the second semiconductor layer opposite to the first semiconductor layer;

wherein the forming of the trenches comprises:

a first step of etching partial trenches crossing the active stack across its entire height and emerging onto the upper surface of the first or second metal layer; and

a second etch step during which the partial trenches are continued through the first and second metal layers.

2. The method of claim 1 , wherein the insulating layer comprises a first portion deposited on the sides of the partial trenches, between the first and second etch steps, and a second portion deposited on the sides of the trenches after the second etch step.

3. The method of claim 1 , wherein, at step d), the partial removal of the insulating layer is performed by anisotropic etching.

4. The method of claim 1 , wherein, during the implementation of step a), the active stack is supported by a support substrate located on the side of the first semiconductor layer opposite to the second semiconductor layer, the method further comprising, between step a) and step b), a step of removing the support substrate.

5. The method of claim 1 , wherein the metallization formed at step e) entirely fills the trenches.

6. The method of claim 1 , wherein said semiconductor diodes are light-emitting diodes.

7. The method of claim 1 , wherein said diodes are photodiodes.

8. The method of claim 1 , wherein the first and second semiconductor layers are gallium nitride layers, said diodes being gallium nitride diodes.

9. The method of claim 1 , wherein the control circuit is formed inside and on top of a semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2020
From: BONO, HUBERT; SIMON, JULIA
To: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES; THALES
Reel/Frame 053137/0865 →
Priority Claims (1)
FR 1760578 · Nov 10, 2017 · national
Continuity (1)
Related Publication 20200335484A1 · Oct 22, 2020
Cited By (1)
US 12,406,974