Display device and method for manufacturing the same

1. A display device comprising:

a lower metal layer disposed on a substrate;

a buffer layer disposed on the lower metal layer;

a first semiconductor layer disposed on the buffer layer;

a gate insulating layer disposed on the first semiconductor layer;

a first gate electrode disposed on the gate insulating layer overlapping the first semiconductor layer;

an interlayer insulating layer disposed on the first gate electrode;

a via layer disposed on the interlayer insulating layer;

a pixel electrode disposed on the via layer and electrically connected to the first semiconductor layer;

a light emitting layer disposed on the pixel electrode;

a common electrode disposed on the light emitting layer;

a first contact hole penetrating the buffer layer and the interlayer insulating layer, and a second contact hole penetrating the interlayer insulating layer; and

a first via hole and a second via hole each penetrating the via layer, wherein

the interlayer insulating layer includes a first upper surface not overlapping the via layer in the first via hole, and

the pixel electrode is electrically connected to the lower metal layer through the first contact hole and the first via hole, electrically connected to the first semiconductor layer through the second contact hole and the second via hole, and disposed on an inner peripheral surface of the first via hole, the first upper surface of the interlayer insulating layer, and an inner peripheral surface of the first contact hole.

2. The display device of claim 1 , wherein the pixel electrode contacts the inner peripheral surface of the first via hole, the first upper surface of the interlayer insulating layer, and the inner peripheral surface of the first contact hole.

3. The display device of claim 1 , wherein

the first contact hole overlaps the first via hole, and

the second contact hole overlaps the second via hole.

4. The display device of claim 3 , wherein the first via hole exposes the first upper surface of the interlayer insulating layer surrounding the first contact hole.

5. The display device of claim 4 , wherein a diameter of the first via hole is larger than a diameter of the first contact hole on a plane where the via layer and the interlayer insulating layer contact each other.

6. The display device of claim 1 , wherein

the interlayer insulating layer includes a second upper surface in contact with the via layer,

the inner peripheral surface of the first via hole has a first taper angle between the inner peripheral surface of the first via hole and the second upper surface of the interlayer insulating layer,

the inner peripheral surface of the first contact hole has a second taper angle between the inner peripheral surface of the first contact hole and the second upper surface of the interlayer insulating layer, and

the first taper angle is smaller than the second taper angle.

7. The display device of claim 6 , wherein the first taper angle is equal to or greater than about 30 degrees and equal to or less than about 60 degrees.

8. The display device of claim 1 , wherein a surface roughness of the via layer is in a range of about 0.1 nm to about 2 nm.

9. The display device of claim 1 , further comprising:

a data line disposed between the substrate and the buffer layer on the substrate; and

a first bridge electrode disposed on the via layer.

10. The display device of claim 9 , further comprising:

a second semiconductor layer spaced apart from the first semiconductor layer on the buffer layer; and

a second gate electrode disposed on the gate insulating layer,

wherein the gate insulating layer is disposed on the second semiconductor layer.

11. The display device of claim 10 , further comprising:

a third contact hole penetrating the buffer layer and the interlayer insulating layer to expose the data line;

a third via hole penetrating the via layer to expose the third contact hole;

a fourth contact hole penetrating the interlayer insulating layer to expose a portion of the second semiconductor layer; and

a fourth via hole penetrating the via layer to expose the fourth contact hole.

12. The display device of claim 11 , wherein the first bridge electrode is electrically connected to the data line through the third contact hole and the third via hole, and electrically connected to the second semiconductor layer through the fourth contact hole and the fourth via hole.

13. The display device of claim 11 , further comprising:

a fifth contact hole penetrating the interlayer insulating layer to expose another portion of the second semiconductor layer;

a fifth via hole penetrating the via layer to expose the fifth contact hole;

a sixth contact hole penetrating the interlayer insulating layer to expose the first gate electrode;

a sixth via hole penetrating the via layer to expose the sixth contact hole; and

a second bridge electrode disposed on the via layer.

14. The display device of claim 13 , wherein the second bridge electrode is electrically connected to another portion of the second semiconductor layer through the fifth contact hole and the fifth via hole, and electrically connected to the first gate electrode through the sixth contact hole and the sixth via hole.

15. The display device of claim 13 , wherein the pixel electrode, the first bridge electrode, and the second bridge electrode are disposed on a same layer and include a same material.

16. A method for manufacturing a display device, the method comprising:

forming a lower metal layer disposed on a substrate;

forming a buffer layer disposed on the lower metal layer;

forming a first semiconductor layer disposed on the buffer layer;

forming a patterned gate insulating layer and a first gate electrode on the first semiconductor layer;

forming an interlayer insulating layer on the first gate electrode;

forming a via layer on the interlayer insulating layer;

forming a patterned hard mask layer on the via layer;

forming a first via hole by etching the via layer using the patterned hard mask layer as an etching mask;

forming a first contact hole by etching a portion of a first upper surface of the interlayer insulating layer exposed by the first via hole and the buffer layer formed under the interlayer insulating layer;

removing the patterned hard mask layer;

forming a pixel electrode on the via layer, an inner peripheral surface of the first via hole, the first upper surface of the interlayer insulating layer exposed by the first via hole, and an inner peripheral surface of the first contact hole formed in the interlayer insulating layer;

forming a light emitting layer on the pixel electrode; and

forming a common electrode on the light emitting layer.

17. The display device of claim 16 , wherein the steps of etching the via layer, the interlayer insulating layer, and the buffer layer include performing a dry etching process using the patterned hard mask layer.

18. The display device of claim 17 , wherein

the via layer is etched by an isotropic dry etching process, and

the interlayer insulating layer and the buffer layer are etched by an anisotropic dry etching process.

19. The display device of claim 18 , wherein the isotropic dry etching process and the anisotropic dry etching process are performed by using a reaction gas containing fluorine (F) and oxygen (O 2 ).

20. The display device of claim 19 , wherein the anisotropic dry etching process is performed by increasing the content of fluorine (F) and reducing the content of oxygen (O 2 ) in comparison to the isotropic dry etching process.

21. The display device of claim 16 , wherein the patterned hard mask layer includes one selected from the group of consisting of ITO, IZO, IGZO, AlOx, ZrOx and HfOx.