IP Library › Granted Patent US 11,416,408
Granted Patent B2
US 11,416,408 · App. 16/721,716 · Granted Aug 16, 2022

Memory system, memory controller and method for operating memory system

Inventor: Byung Jun Kim (Seoul, KR)
Assignee: SK hynix Inc.
G06F12/0873G06F9/4837G06F9/5016G06F11/3037G06F12/0246G06F13/1668G06F2212/7201
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Quick Facts
Patent No.
US 11,416,408
App. No.
16/721,716
Granted
Aug 16, 2022
Kind
B2
Abstract

A memory controller, a memory system including the memory controller and a method for operating the memory system are disclosed. The memory controller updates a reference parameter for a memory area in which at least part of the mapping information is stored and determines whether to activate the memory area based on the reference parameter to effectively execute commands received from a host.

Claims (38)

1. A memory system comprising a memory device located inside the memory system to store mapping information between logical addresses and physical addresses and a memory controller in communication with the memory device to control the memory device,

wherein the memory controller is in communication with a host that is located outside the memory system and includes a memory area configured to store the mapping information, and wherein the memory controller is configured to:

update a reference parameter for at least part of the mapping information stored in the memory area located in the host, based on workload information associated with a command received from the host; and

determine whether to activate the memory area in the host to store the at least part of the mapping information in the memory area in a case that the reference parameter is equal to or greater than a threshold value or deactivate the memory area in the host in a case that the reference parameter is less than the threshold value,

wherein the host refers to the at least part of the mapping information in the memory area in the host in a case that the memory area is activated, and the host refers to the mapping information in the memory device located inside the memory system without referring to the memory area in the host in a case that the memory area is deactivated.

2. The memory system according to claim 1 , wherein the workload information is determined based on a read command or a write command received from the host for a predetermined time period.

3. The memory system according to claim 2 ,

wherein, upon receipt from the host of a read command referring to the mapping information stored in the memory area, the memory controller updates a value of the reference parameter to increase an activation possibility of the memory area, and

wherein, upon receipt from the host of a write command for a logical address corresponding to the mapping information stored in the memory area, the memory controller updates a value of the reference parameter to decrease an activation possibility of the memory area.

4. The memory system according to claim 1 , wherein the workload information is determined based on a pattern of logical addresses corresponding to one or more commands received from the host for a predetermined time period.

5. The memory system according to claim 4 ,

wherein, when the pattern of logical addresses is a random pattern, the memory controller updates a value of the reference parameter to increase an activation possibility of the memory area, and

wherein, when the pattern of logical addresses is a sequential pattern, the memory controller updates a value of the reference parameter to decrease an activation possibility of the memory area.

6. The memory system according to claim 1 , wherein the workload information is determined based on a frequency of referring to the memory area responsive to commands received from the host for a predetermined time period.

7. The memory system according to claim 6 ,

wherein, when the frequency of referring to the memory area is equal to or greater than a threshold frequency, the memory controller updates a value of the reference parameter to increase an activation possibility of the memory area, and

wherein, when the frequency of referring to the memory area is less than the threshold frequency, the memory controller updates a value of the reference parameter to decrease an activation possibility of the memory area.

8. The memory system according to claim 1 , wherein, when the memory area is in a deactivated state, the memory controller updates the reference parameter based on whether a logical address included in a command received from the host matches a logical address included in mapping information stored in a virtual memory area positioned in the memory controller.

9. The memory system according to claim 8 , wherein the memory controller deactivates the virtual memory area when the memory area is converted into an activated state from the deactivated state.

10. A memory controller comprising: a memory interface for communicating with a memory device located inside a memory system and configured to store mapping information between logical addresses and physical addresses and a control circuit including a processor for controlling the memory device and for communicating with a host that is located outside the memory system and includes a memory area configured to store the mapping information,

wherein the control circuit is configured to:

update a reference parameter for at least part of the mapping information stored in the memory area located in the host, based on workload information associated with a command received from the host; and

determine whether to activate the memory area in the host to store the at least part of the mapping information in the memory area in a case that the reference parameter is equal to or greater than a threshold value or deactivate the memory area in the host in a case that the reference parameter is less than the threshold value,

wherein the host refers to the at least part of the mapping information in the memory area in the host in a case that the memory area is activated, and the host refers to the mapping information in the memory device located inside the memory system without referring to the memory area in the host in a case that the memory area is deactivated.

11. The memory controller according to claim 10 , wherein the workload information is determined based on a read command or a write command received from the host for a predetermined time period.

12. The memory controller according to claim 10 , wherein the workload information is determined based on a pattern of logical addresses corresponding to one or more commands received from the host for a predetermined time period.

13. The memory controller according to claim 10 , wherein the workload information is determined based on a frequency of referring to the memory area responsive to commands received from the host for a predetermined time period.

14. The memory controller according to claim 10 , wherein, when the memory area is in a deactivated state, the control circuit updates the reference parameter based on whether a logical address included in a command received from the host matches a logical address included in mapping information stored in a virtual memory area positioned in the memory controller.

15. The memory controller according to claim 14 , wherein the control circuit deactivates the virtual memory area when the memory area is converted into an activated state from the deactivated state.

16. A method for operating a memory system, comprising:

updating, by a first device which is located inside the memory system and in communication with a second device that is located outside the memory system and includes a memory area configured to store the mapping information, a reference parameter associated with the memory area located in the second device in which at least part of mapping information for mapping between logical addresses and physical addresses is stored, based on workload information on a command received from the second device different from the first device; and

determining, by the first device, whether to activate the memory area in the second device in a case that the reference parameter is equal to or greater than a threshold value or deactivate the memory area in the second device in a case that the reference parameter is less than the threshold area,

wherein the second device refers to at least part of the mapping information in the memory area located in the second device in a case that the memory area located in the second device is activated, and the second device refers to the mapping information in the memory system in a case that the memory area located in the second device is deactivated, and

wherein the second device includes the memory area.

17. The method according to claim 16 , wherein the first device includes a memory controller included in the memory system, and the second device includes a host configured to transmit a command to the memory controller.

18. The method according to claim 17 , wherein the workload information is determined based on a read command or a write command received from the host for a predetermined time period.

19. The method according to claim 17 , wherein the workload information is determined based on a pattern of logical addresses corresponding to one or more commands received from the host for a predetermined time period.

20. The method according to claim 17 , wherein the workload information is determined based on a frequency of referring to the memory area responsive to commands received from the host for a predetermined time period.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2019
From: KIM, BYUNG JUN
To: SK HYNIX INC.
Reel/Frame 051338/0902 →
Priority Claims (1)
KR 10-2019-0081023 · Jul 5, 2019 · national
Continuity (1)
Related Publication 20210004330A1 · Jan 7, 2021