Electrostatic discharge protection structure in a semiconductor device

1. An electrostatic discharge protection structure comprising:

a laterally diffused metal oxide semiconductor (LDMOS) device, the LDMOS device comprising an embedded PNP bipolar junction transistor, wherein

a gate, a source, a buried layer lead-out area, and a substrate lead-out area of the LDMOS device are connected to a ground,

a drain and a body region lead-out area of the LDMOS device are directly connected to a pad input/output terminal, wherein the source, the body region lead-out area, the buried layer lead-out area, and the substrate lead-out area are arranged sequentially away from the gate and isolated from each other by a STI structure,

the embedded PNP bipolar junction transistor is operative to transmit a reverse electrostatic discharge current while the drain, the gate, the source, and the substrate lead-out area form a grounded-gate NMOS (GGNMOS) being operative to transmit a forward electrostatic discharge current,

a base and an emitter of the embedded PNP bipolar junction transistor are directly connected to the ground, and

the LDMOS device comprises:

a P-type substrate;

an N-type buried layer formed in the P-type substrate;

an epitaxial layer formed on the N-type buried layer;

an N deep well, a first P deep well, and a second P deep well formed in the epitaxial layer;

a first P well and an N-type drift region completely embedded in the first P deep well, the first P well and the N-type drift region separated from each other;

a P+ body region lead-out area and an N+ source formed in the first P well;

an N+ drain formed in the N-type drift region;

an N well completely embedded in the N deep well;

an N+ buried layer lead-out area formed in the N well;

a second P well completely embedded in the second P deep well;

a P+ substrate lead-out area formed in the second P well; and

a gate electrode formed on the epitaxial layer between the first P well and the N-type drift region.

2. The electrostatic discharge protection structure of claim 1 , wherein the LDMOS device comprises an n-type LDMOS device.

3. The electrostatic discharge protection structure of claim 1 , wherein the P+ body region lead-out area forms a collector of the PNP bipolar junction transistor, the N+ buried layer lead-out area forms the base of the PNP bipolar junction transistor, and the P+ substrate lead-out area forms the emitter of the PNP bipolar junction transistor.

4. The electrostatic discharge protection structure of claim 1 , wherein:

the N-type drift region is formed in the first P deep well on a first side of the gate and the first P well is formed in the first P deep well on a second side of the gate opposite to the first side of the gate,

the N deep well is further away from the gate than the first P well on the second side of the gate, and

the second P deep well is further away from the gate than the N deep well on the second side of the gate.

5. An electronic apparatus comprising:

an electrostatic discharge protection structure; and

an electronic component assembly coupled to the electrostatic discharge protection structure;

wherein the electrostatic discharge protection structure comprises a laterally diffused metal oxide semiconductor (LDMOS) device comprising an embedded PNP bipolar junction transistor, and wherein a gate, a source, a buried layer lead-out area, and a substrate lead-out area of the LDMOS device are connected to a ground, a drain and a body region lead-out area of the LDMOS device are directly connected to a pad input/output terminal, wherein the source, the body region lead-out area, the buried layer lead-out area, and the substrate lead-out area are arranged sequentially away from the gate and isolated from each other by a STI structure, the embedded PNP bipolar junction transistor is operative to transmit a reverse electrostatic discharge current while the drain, the gate, the source, and the substrate lead-out area form a grounded-gate NMOS (GGNMOS) being operative to transmit a forward electrostatic discharge current, and a base and an emitter of the embedded PNP bipolar junction transistor are directly connected to the ground, and

wherein the LDMOS device comprises:

a P-type substrate;

an N-type buried layer formed in the P-type substrate;

an epitaxial layer formed on the N-type buried layer;

an N deep well, a first P deep well, and a second P deep well formed in the epitaxial layer;

a first P well and an N-type drift region completely embedded in the first P deep well, the first P well and the N-type drift region separated from each other;

a P+ body region lead-out area and an N+ source formed in the first P well;

an N+ drain formed in the N-type drift region;

an N well completely embedded in the N deep well;

an N+ buried layer lead-out area formed in the N well;

a second P well completely embedded in the second P deep well;

a P+ substrate lead-out area formed in the second P well; and

a gate electrode formed on the epitaxial layer between the first P well and the N-type drift region.

6. The electrostatic discharge protection structure of claim 5 , wherein the embedded PNP bipolar junction transistor comprises a collector connected to the pad input/output terminal.

7. The electronic apparatus of claim 5 , wherein the P+ body region lead-out area forms a collector of the PNP bipolar junction transistor, the N+ buried layer lead-out area forms the base of the PNP bipolar junction transistor, and the P+ substrate lead-out area forms the emitter of the PNP bipolar junction transistor.

8. The electronic apparatus of claim 5 , wherein the N+ drain, the gate, the N+ source, and the P+ substrate lead-out area form a grounded-gate NMOS (GGNMOS).

9. The electronic apparatus of claim 8 , wherein the PNP bipolar junction transistor is operative to transmit a reverse electrostatic discharge current, and the GGNMOS is operative to transmit a forward electrostatic discharge current.

10. An electrostatic discharge protection structure, comprising:

a laterally diffused metal oxide semiconductor (LDMOS) device having an embedded PNP transistor, wherein the LDMOS device comprises a gate and a source both directly connected to a ground, and a drain directly connected to a pad input/output terminal, wherein the source, the body region lead-out area, the buried layer lead-out area, and the substrate lead-out area are arranged sequentially away from the gate and isolated from each other by a STI structure, the embedded PNP bipolar junction transistor is operative to transmit a reverse electrostatic discharge current while the drain, the gate, the source, and the substrate lead-out area form a grounded-gate NMOS (GGNMOS) being operative to transmit a forward electrostatic discharge current, and the embedded PNP transistor comprises a base and an emitter directly connected to the ground, wherein the LDMOS device comprises:

a P-type substrate;

an N-type buried layer formed in the P-type substrate;

an epitaxial layer formed on the N-type buried layer;

an N deep well, a first P deep well, and a second P deep well formed in the epitaxial layer;

a first P well and an N-type drift region completely embedded in the first P deep well, the first P well and the N-type drift region separated from each other;

a P+ body region lead-out area and an N+ source formed in the first P well;

an N+ drain formed in the N-type drift region;

an N well completely embedded in the N deep well;

an N+ buried layer lead-out area formed in the N well;

a second P well completely embedded in the second P deep well;

a P+ substrate lead-out area formed in the second P well; and

a gate electrode formed on the epitaxial layer between the first P well and the N-type drift region.

11. The electrostatic discharge protection structure of claim 10 , wherein:

the N+ buried layer lead-out area forms the base of the embedded PNP transistor;

the P+ substrate lead-out area forms the emitter of the embedded PNP transistor; and

the P+ body region lead-out area forms a collector of the embedded PNP transistor.

12. The electrostatic discharge protection structure of claim 10 , wherein the gate of the LDMOS device is disposed on the epitaxial layer between the first P well and the N-type drift region.