Semiconductor memory device

1. A semiconductor memory device comprising:

a first conductive layer;

a stacked body that is arranged above the first conductive layer and includes a plurality of second conductive layers stacked with a first insulating layer interposed therebetween;

a pillar that extends in the stacked body in a stacking direction of the stacked body, reaches a first position in the first conductive layer, the first position being deeper than a position of an upper surface of the first conductive layer, and includes a plurality of memory cells at intersections with at least some of the plurality of second conductive layers; and

a first structure that extends in the stacked body in a first direction orthogonal to the stacking direction and in the stacking direction, and reaches a second position in the first conductive layer, the second position being deeper than the position of the upper surface of the first conductive layer, wherein

the first structure has a width in a second direction orthogonal to the stacking direction and the first direction, the width including a first width at a bottom of the stacked body and a second width that is narrower than the first width, in a first depth region from the position of the upper surface of the first conductive layer to a first depth position that is deeper than the position of the upper surface in the first conductive layer, and

the first structure includes a third conductive layer that extends in the first structure in the first direction and the stacking direction and is connected to a side surface of the first conductive layer in the second direction in the first depth region.

2. The semiconductor memory device according to claim 1 , wherein the second width of the first structure decreases from upper to lower in the first depth region.

3. The semiconductor memory device according to claim 1 , wherein

the first conductive layer projects than the stacked body toward a central part of the first structure in the second direction in the first depth region, and

the third conductive layer is also connected to the projecting upper surface of the first conductive layer.

4. The semiconductor memory device according to claim 3 , wherein the projecting upper surface of the first conductive layer is inclined in such a direction that a depth increases toward the central part of the first structure in the second direction.

5. The semiconductor memory device according to claim 1 , wherein the first structure further includes a second insulating layer interposed between the first conductive layer and the third conductive layer in a second depth region deeper than the first depth region while covering a bottom of the first structure.

6. The semiconductor memory device according to claim 5 , wherein

the second insulating layer covering the bottom of the first structure has a recess, and

the third conductive layer projects into the recess.

7. The semiconductor memory device according to claim 1 , wherein the third conductive layer is connected to the first conductive layer also at a bottom of the first structure.

8. The semiconductor memory device according to claim 1 , wherein the pillar includes a semiconductor layer that extends in the stacking direction in the stacked body and is connected to the first conductive layer at a third depth region deeper than the first depth region in the first conductive layer.

9. The semiconductor memory device according to claim 8 , wherein the first conductive layer is connected to an outer peripheral surface of the semiconductor layer in the third depth region.

10. The semiconductor memory device according to claim 1 , further comprising a peripheral circuit that includes a transistor disposed below the first conductive layer and contributes to an operation of the memory cells.

11. A semiconductor memory device comprising:

a first conductive layer;

a stacked body that is arranged above the first conductive layer and includes a plurality of second conductive layers stacked with a first insulating layer interposed therebetween;

a pillar that extends in the stacked body in a stacking direction of the stacked body, reaches a first position in the first conductive layer, the first position being deeper than a position of an upper surface of the first conductive layer, and includes a plurality of memory cells at intersections with at least some of the plurality of second conductive layers; and

a first structure that extends in the stacked body in a first direction orthogonal to the stacking direction and in the stacking direction, and reaches a second position in the first conductive layer, the second position being deeper than the position of the upper surface of the first conductive layer, wherein

the first structure includes:

a third conductive layer that extends in the first structure in the first direction and the stacking direction and is connected to a side surface of the first conductive layer in a first depth region in a second direction orthogonal to the stacking direction and the first direction; and

a second insulating layer interposed between the first conductive layer and the third conductive layer in a second depth region deeper than the first depth region while covering a bottom of the first structure.

12. The semiconductor memory device according to claim 11 , wherein the first structure has a width in the second direction, the width including a first width at a bottom of the stacked body, a second width in the first depth region, and a third width in the second depth region, respectively, the second width being narrower than the first width, the second width being narrower than the third width at a depth position of a boundary between the first depth region and the second depth region.

13. The semiconductor memory device according to claim 12 , wherein the second width of the first structure decreases from upper to lower in the first depth region.

14. The semiconductor memory device according to claim 12 , wherein

the first conductive layer projects than the stacked body toward a central part of the first structure in the second direction in the first depth region, and

the third conductive layer is also connected to the projecting upper surface of the first conductive layer.

15. The semiconductor memory device according to claim 14 , wherein the projecting upper surface of the first conductive layer is inclined in such a direction that a depth increases toward the central part of the first structure in the second direction.

16. The semiconductor memory device according to claim 11 , wherein

the second insulating layer covering the bottom of the first structure has a recess, and

the third conductive layer projects into the recess.

17. The semiconductor memory device according to claim 16 , wherein

the recess penetrates the second insulating layer, and

the third conductive layer projecting into the recess is also connected to the first conductive layer at the bottom of the first structure.

18. The semiconductor memory device according to claim 11 , wherein the pillar includes a semiconductor layer that extends in the stacking direction in the stacked body and is connected to the first conductive layer at a third depth region deeper than the first depth region in the first conductive layer.

19. The semiconductor memory device according to claim 18 , wherein the first conductive layer is connected to an outer peripheral surface of the semiconductor layer in the third depth region.

20. The semiconductor memory device according to claim 11 , further comprising a peripheral circuit that includes a transistor disposed below the first conductive layer and contributes to an operation of the memory cell.