IP Library › Granted Patent US 11,417,811
Granted Patent B2
US 11,417,811 · App. 16/717,305 · Granted Aug 16, 2022

Light emitting element, light emitting device, and method for manufacturing light emitting element

Inventors: Koichi Takenaga (Tokushima, JP); Takanori Fukumori (Tokushima, JP); Satoshi Shichijo (Tokushima, JP); Hiroki Fukuta (Anan, JP); Kunihito Sugimoto (Anan, JP)
Assignee: NICHIA CORPORATION
H01L33/62H01L27/153H01L33/0075H01L33/20H01L33/32H01L33/38H01L33/382H01L33/405H01L33/44H01L33/56H01L33/60H01L33/647H01L25/0753H01L2933/0016H01L2933/0025
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Quick Facts
Patent No.
US 11,417,811
App. No.
16/717,305
Granted
Aug 16, 2022
Kind
B2
Abstract

A light emitting element includes a semiconductor stacked body, an insulating film, first and second electrodes, a second external connection portion, and first external connection portions. The first semiconductor layer is exposed at a plurality of exposed portions disposed in a plurality of rows in plan view. The first external connection portions include at least one smaller-size first external connection portion disposed between adjacent ones of the rows other than the outermost one of the rows, and at least one larger-size first external connection portion extending from the end region, in which a spacing between a first outer edge of a second semiconductor layer and the exposed portions in the outermost one of the rows is narrower than a spacing between the exposed portions in adjacent ones of the rows, to at least a position between the outermost one of the rows and an adjacent one of the rows.

Claims (46)

1. A light emitting element comprising:

a semiconductor stacked body having

a first semiconductor layer,

a light emitting layer stacked on the first semiconductor layer, and

a second semiconductor layer stacked on the light emitting layer,

on a second semiconductor layer side of the semiconductor stacked body, the first semiconductor layer is exposed from the second semiconductor layer and the light emitting layer at a plurality of exposed portions, the exposed portions being disposed in a plurality of rows in plan view with each of the rows extending in a first direction and the rows being aligned along a second direction perpendicular to the first direction, and

the semiconductor stacked body having an end region in which a spacing along the second direction between a first outer edge of the second semiconductor layer extending along the first direction and the exposed portions in an outermost one of the rows closest to the first outer edge of the second semiconductor layer is narrower than a spacing along the second direction between the exposed portions in adjacent ones of the rows;

an insulating film covering the semiconductor stacked body and defining a plurality of openings respectively above the exposed portions;

a first electrode connected to the exposed portions at the openings in the insulating film, the first electrode being partly disposed over the second semiconductor layer via the insulating film;

a second electrode connected to the second semiconductor layer;

a second external connection portion connected to the second electrode; and

a plurality of first external connection portions connected to the first electrode, the first external connection portions being spaced apart from the exposed portions in the plan view with each of the first external connection portions extending in the first direction between corresponding adjacent ones of the rows of the exposed portions, the first external connection portions including at least one smaller-size first external connection portion disposed between adjacent ones of the rows of the exposed portions other than the outermost one of the rows, and at least one larger-size first external connection portion extending from the end region to at least a position between the outermost one of the rows and an adjacent one of the rows the exposed portions, the at least one larger-size first external connection portion has a larger surface area than the at least one smaller-size first external connection portion in the plan view.

2. The light emitting element according to claim 1 , wherein

the at least one larger-size first external connection portion surrounds the exposed portions in the outermost one of the rows in the plan view.

3. The light emitting element according to claim 1 , wherein

the at least one larger-size first external connection portion defines at least one first groove that extends in the second direction from one of the exposed portions in the outermost one of the rows toward the first outer edge of the second semiconductor layer in the plan view.

4. The light emitting element according to claim 3 , wherein

a width of the at least one first groove along the first direction is less than a width of the one of the exposed portions along the first direction in the plan view.

5. A light emitting device comprising:

a substrate having a wiring pattern on an upper surface;

the light emitting element according to claim 1 , the light emitting element being flip-chip mounted on the wiring pattern; and

a cover member containing a light reflecting material and covering the light emitting element, the first external connection portions, the second external connection portion and the substrate.

6. A light emitting device comprising:

a substrate having a wiring pattern on an upper surface;

the light emitting element according to claim 2 , the light emitting element being flip-chip mounted on the wiring pattern; and

a cover member containing a light reflecting material, and covering the light emitting element, the first external connection portions, the second external connection portion and the substrate.

7. A light emitting device comprising:

a substrate having a wiring pattern on an upper surface;

the light emitting element according to claim 3 , the light emitting element being flip-chip mounted on the wiring pattern; and

a cover member containing a light reflecting material, and covering the light emitting element, the first external connection portions, the second external connection portion and the substrate.

8. The light emitting element according to claim 1 , wherein

the at least one larger-size external connection portion defines at least one groove that extends in the first direction from one of the exposed portions in the outermost one of the rows closest to the first outer edge of the second semiconductor layer toward a second outer edge of the second semiconductor layer extending along the second direction, in plan view.

9. The light emitting element according to claim 3 , wherein

the at least one larger-size external connection portion defines at least one second groove that extends in the first direction from one of the exposed portions in the outermost one of the rows closest to the first outer edge of the second semiconductor layer toward a second outer edge of the second semiconductor layer extending along the second direction, in plan view.

10. The light emitting element according to claim 8 , wherein

a width of the at least one groove is less than a width of the exposed portion, in plan view.

11. The light emitting element according to claim 9 , wherein

a width of the at least one second groove is less than a width of the exposed portion, in plan view.

12. The light emitting element according to claim 9 , wherein

a number of the at least one first groove is more than a number of the at least one second groove.

13. The light emitting element according to claim 11 , wherein

a number of the at least one first groove is more than a number of the at least one second groove.

14. A light emitting device, comprising:

a substrate having a wiring pattern on an upper surface;

the light emitting element according to claim 9 , the light emitting element being flip-chip mounted on the wiring pattern; and

a cover member containing a light reflecting material and covering the light emitting element, the first external connection portions, the second external connection portion and the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2019
From: TAKENAGA, KOICHI; FUKUMORI, TAKANORI; SHICHIJO, SATOSHI; FUKUTA, HIROKI; SUGIMOTO, KUNIHITO
To: NICHIA CORPORATION
Reel/Frame 051307/0619 →
Priority Claims (1)
JP JP2018-247571 · Dec 28, 2018 · national
Continuity (1)
Related Publication 20200212278A1 · Jul 2, 2020
Cited By (1)
US 12,439,751