Equalizer and communication module using the same
An equalizer has a first tapped delay line in which N taps (N is a positive integer) are connected in cascade, a second tapped delay line having one tap and connected in parallel with the first tapped delay line, a first multiplier configured to multiply signals extracted from the N taps by corresponding coefficients, a second multiplier configured to multiply a signal output from the second tapped delay line by a second coefficient, and an adder configured to add products of the first multiplier and a product of the second multiplier. The first tapped delay line has a fixed delay, and the second tapped delay line has a variable delay changeable at a 1/M resolution of the fixed delay, where M is a number greater than 1.
1. An equalizer comprising:
a first tapped delay line in which N taps are connected in cascade, where N is a positive integer;
a second tapped delay line connected in parallel with the first tapped delay line, the second tapped delay line having one tap;
a first multiplier configured to multiply signals extracted from the N taps by corresponding coefficients;
a second multiplier configured to multiply a signal output from the second tapped delay line by a second coefficient; and
an adder configured to add products of the first multiplier and a product of the second multiplier,
wherein the first tapped delay line has a fixed delay, and the second tapped delay line has a variable delay changeable at a 1/M resolution of the fixed delay, where M is a number greater than 1, and
wherein the variable delay is expressed as
τ×(L+1/M)
where τ is the fixed delay set between any two adjacent taps of the N taps, and L is an integer greater than or equal to zero.
2. The equalizer as claimed in claim 1 , where the second multiplier is connected to an output of the variable delay.
3. The equalizer as claimed in claim 1 , wherein the first multiplier includes N multipliers respectively connected to the N taps.
4. An equalizer comprising
a first tapped delay line in which N taps are connected in cascade, where N is a positive integer;
a second tapped delay line connected in parallel with the first tapped delay line, the second tapped delay line having one tap;
a first multiplier configured to multiply signals extracted from the N taps by corresponding coefficients;
a second multiplier configured to multiply a signal output from the second tapped delay line by a second coefficient;
an adder configured to add products of the first multiplier and a product of the second multiplier; and
N switches connected between the second tapped delay line and the N taps,
wherein the first tapped delay line has a fixed delay, and the second tapped delay line has a variable delay changeable at a 1/M resolution of the fixed delay, where M is a number greater than 1, and
wherein any one of the N switches is selectable.
5. The equalizer as claimed in claim 4 , wherein the variable delay varies from τ/M to (N−1)×τ÷τ/M, depending on a switch selected, where τ is the fixed delay set between any two adjacent taps of the N taps.
6. A communication module comprising:
a digital signal processor having an equalizer; and
an assembly or a part connected to the digital signal processor,
wherein the equalizer includes
a first tapped delay line in which N taps are connected in cascade, where N is a positive integer,
a second tapped delay line connected in parallel with the first tapped delay line, the second tapped delay line having one tap,
a first multiplier configured to multiply signals extracted from the N taps by corresponding coefficients,
a second multiplier configured to multiply a signal output from the second tapped delay line by a second coefficient, and
an adder configured to add products of the first multiplier and a product of the second multiplier,
wherein the first tapped delay line has a fixed delay, and the second tapped delay line has a variable delay changeable at a 1/M resolution of the fixed delay, where M is a number greater than 1, and
wherein a value of the variable delay is determined in accordance with a reflection generated between the digital signal processor and the assembly or the part,
wherein the assembly or the part is a modulator driver or an optical modulator, and
wherein the value of the variable delay is determined according to a transmission delay time between the digital signal processor and the modulator driver, or a transmission delay time between the modulator driver and the optical modulator.
7. A communication comprising:
a digital signal processor having an equalizer; and
an assembly or a part connected to the digital signal processor,
wherein the equalizer includes
a first tapped delay line in which N taps are connected in cascade, where N is a positive integer,
a second tapped delay line connected in parallel with the first tapped delay line, the second tapped delay line having one tap,
a first multiplier configured to multiply signals extracted from the N taps by corresponding coefficients,
a second multiplier configured to multiply a signal output from the second tapped delay line by a second coefficient, and
an adder configured to add products of the first multiplier and a product of the second multiplier,
wherein the first tapped delay line has a fixed delay, and the second tapped delay line has a variable delay changeable at a 1/M resolution of the fixed delay, where M is a number greater than 1,
wherein a value of the variable delay is determined in accordance with a reflection generated between the digital signal processor and the assembly or the part,
wherein the assembly or the part is an optical-to-electrical circuit, and
wherein the value of the variable delay is determined according to a transmission delay time between the digital signal processor and the optical-to-electrical circuit.