AC coupling modules for bias ladders
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V GS type, or a mix of positive-logic and zero V GS type FETs with end-cap FETs of the zero V GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.
1. A FET switch stack, including:
(a) a plurality of series-coupled FETs defining a signal path and including one or more series-coupled positive-logic FETs requiring a relative negative V GS to effectively turn OFF but configured to not require a negative voltage source;
(b) a first end-cap FET that turns OFF when the V GS of such first end-cap FET is essentially zero volts, series-coupled to a first end of the plurality of series-coupled FETs in the signal path and configured to selectably provide either a capacitive DC blocking function or a resistive signal path;
(c) a gate bias resistor ladder including a plurality of resistors configured to be coupled to a gate bias voltage and to the gate of at least one corresponding series-coupled FET or the first end-cap FET; and
(d) a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage and to the body of at least one corresponding series-coupled FET;
wherein the resistors of the gate bias resistor ladder are series-connected and the resistors of the body charge control resistor ladder are parallel-connected.
2. The invention of claim 1 , further including a second end-cap FET that turns OFF when the V GS of such second end-cap FET is essentially zero volts, series-coupled to a second end of the plurality of series-coupled FETs in the signal path and configured to selectably provide either a capacitive DC blocking function or a resistive signal path.
3. The invention of claim 1 , further including an AC coupling gate module coupled to at least one end of the gate bias resistor ladder and configured to be coupled to a radio frequency voltage source.
4. The invention of claim 3 , wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor.
5. The invention of claim 1 , further including an AC coupling body module coupled to at least one end of the body charge control resistor ladder and configured to be coupled to a radio frequency voltage source.
6. The invention of claim 5 , wherein the AC coupling body module includes one of a capacitor or a capacitor series coupled to a resistor.
7. The invention of claim 1 , further including a capacitor coupled between the gate bias resistor ladder and a reference potential.
8. The invention of claim 1 , further including a capacitor coupled between the body charge control resistor ladder and a reference potential.
9. The invention of claim 1 , further including a parallel-connected gate resistor ladder, including a plurality of resistors each coupled between the gate bias resistor ladder and the gate of a corresponding FET.
10. The invention of claim 1 , further including a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of at least one corresponding adjacent series-coupled FET.
11. A FET switch stack, including:
(a) a plurality of series-coupled FETs defining a signal path and including one or more series-coupled positive-logic FETs requiring a relative negative V GS to effectively turn OFF but configured to not require a negative voltage source;
(b) a first end-cap FET that turns OFF when the V GS of such first end-cap FET is essentially zero volts, series-coupled to a first end of the plurality of series-coupled FETs in the signal path and configured to selectably provide either a capacitive DC blocking function or a resistive signal path;
(c) a gate bias resistor ladder including a plurality of resistors configured to be coupled to a gate bias voltage and to the gate of at least one corresponding series-coupled FET or the first end-cap FET; and
(d) a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage and to the body of at least one corresponding series-coupled FET;
wherein the resistors of the gate bias resistor ladder are parallel-connected and the resistors of the body charge control resistor ladder are series-connected.
12. The invention of claim 11 , further including a second end-cap FET that turns OFF when the V GS of such second end-cap FET is essentially zero volts, series-coupled to a second end of the plurality of series-coupled FETs in the signal path and configured to selectably provide either a capacitive DC blocking function or a resistive signal path.
13. The invention of claim 11 , further including an AC coupling gate module coupled to at least one end of the gate bias resistor ladder and configured to be coupled to a radio frequency voltage source.
14. The invention of claim 13 , wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor.
15. The invention of claim 11 , further including an AC coupling body module coupled to at least one end of the body charge control resistor ladder and configured to be coupled to a radio frequency voltage source.
16. The invention of claim 15 , wherein the AC coupling body module includes one of a capacitor or a capacitor series coupled to a resistor.
17. The invention of claim 11 , further including a capacitor coupled between the gate bias resistor ladder and a reference potential.
18. The invention of claim 11 , further including a capacitor coupled between the body charge control resistor ladder and a reference potential.
19. The invention of claim 11 , further including a series-connected gate resistor ladder, including a plurality of resistors configured to be coupled to a gate bias voltage, each resistor configured to be coupled to a corresponding resistor of the gate bias resistor ladder.
20. The invention of claim 11 , further including a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of at least one corresponding adjacent series-coupled FET.