IP Library › Granted Patent US 11,418,671
Granted Patent B2
US 11,418,671 · App. 16/569,869 · Granted Aug 16, 2022

Information processing apparatus, and method of controlling the same

Inventor: Shinichi Ono (Tokyo, JP)
Assignee: Canon Kabushiki Kaisha
H04N1/00928G06F11/1417G06F13/4282G06F21/572G06F21/575H04L9/3236H04N1/00896H04N1/00925G06F2221/033H04N2201/0094
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Quick Facts
Patent No.
US 11,418,671
App. No.
16/569,869
Filed
Sep 13, 2019
Granted
Aug 16, 2022
Kind
B2
Art Unit
2115
USPC
713/2
Abstract

An information processing apparatus includes a storage unit in which a boot program is stored, a first control unit and a second control unit. The first control unit validates the boot program stored in the storage unit and transmits a pattern signal indicating that the boot program stored in the storage unit is validated. The second control unit executes the boot program stored in the storage unit in accordance with the pattern signal received from the first control unit.

Claims (39)

1. An information processing apparatus comprising:

a storage unit in which a boot program is stored;

a first control unit configured to, upon release of a reset state of the first control unit, validate the boot program stored in the storage unit and transmit a pattern signal indicating that the boot program stored in the storage unit is validated; and

a second control unit configured to, upon release of a reset state of the second control unit, transition to a state of waiting for reception of the pattern signal, and start execution of the boot program stored in the storage unit in accordance with reception of the pattern signal from the first control unit.

2. The apparatus according to claim 1 , wherein the pattern signal is a signal combining one or more high levels and one or more low levels.

3. The apparatus according to claim 1 , wherein

the second control unit includes a non-rewritable memory area in which a program is stored, and

upon release of the reset state of the second control unit, the second control unit transitions to the state of waiting for reception of the pattern signal by executing the program stored in the non-rewritable memory area and then starts execution of the boot program stored in the storage unit in accordance with reception of the pattern signal from the first control unit.

4. The apparatus according to claim 3 , wherein the program stored in the non-rewritable memory area is executed first by the second control unit after the apparatus is activated from a power-off state.

5. The apparatus according to claim 1 , wherein the first control unit notifies of error of the boot program if the boot program stored in the storage unit is not validated.

6. The apparatus according to claim 1 , wherein the second control unit transmits a reception confirmation signal to the first control unit in accordance with reception of another pattern signal indicating that the boot program stored in the storage unit is validated, and executes the boot program in accordance with reception of the pattern signal as response of the reception confirmation signal.

7. The apparatus according to claim 1 , further comprising:

a reset unit configured to reset the second control unit and, if the apparatus is activated from a power-off state, release the reset state of the second control unit.

8. The apparatus according to claim 7 , wherein the reset unit is further configured to reset the first control unit and, if the apparatus is activated from the power-off state, release the reset state of the first control unit.

9. The apparatus according to claim 1 , further comprising:

a memory in which encrypted information obtained from the boot program is stored in advance,

wherein the first control unit validates the boot program by comparing a hash value obtained by decrypting the encrypted information stored in the memory with a hash value of the boot program stored in the storage unit.

10. The apparatus according to claim 1 , wherein the first control unit transitions to a power saving state after transmitting the pattern signal to the second control unit.

11. The apparatus according to claim 1 , wherein the first control unit accesses the boot program stored in the storage unit via a first interface and transmits the pattern signal to the second control unit via a second interface.

12. The apparatus according to claim 11 , wherein the first interface is a SPI (Serial Peripheral Interface) interface.

13. The apparatus according to claim 11 , wherein the second interface is a GPIO (General-purpose input/output).

14. The apparatus according to claim 1 , further comprising:

a printing unit configured to print image.

15. The apparatus according to claim 1 , further comprising:

a scanner unit configured to scan image.

16. A method of controlling an information processing apparatus that comprises a storage unit in which a boot program is stored, a first control unit and a second control unit, the method comprising:

upon release of a reset state of the first control unit, the first control unit validating the boot program stored in the storage unit and transmitting a pattern signal indicating that the boot program stored in the storage unit is validated;

upon release of a reset state of the second control unit, the second control unit transitioning to a state of waiting for reception of the pattern signal; and

the second control unit starting execution of the boot program stored in the storage unit in accordance with reception of the pattern signal from the first control unit.

17. The method according to claim 16 , wherein

the pattern signal is a signal combining one or more high levels and one or more low levels.

18. The method according to claim 16 , wherein

the second control unit includes a non-rewritable memory area in which a program is stored, and

upon release of the reset state of the second control unit, the second control unit transitions to the state of waiting for reception of the pattern signal by executing the program stored in the non-rewritable memory area and then starts execution of the boot program stored in the storage unit in accordance with reception of the pattern signal from the first control unit.

19. The method according to claim 16 , further comprising:

the first control unit notifying of error of the boot program if the boot program stored in the storage unit is not validated.

20. The method according to claim 16 , wherein

the information processing apparatus further comprises a memory in which encrypted information obtained from the boot program is stored in advance, and

the boot program is validated by comparing a hash value obtained by decrypting the encrypted information stored in the memory with a hash value of the boot program stored in the storage unit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2019
From: ONO, SHINICHI
To: CANON KABUSHIKI KAISHA
Reel/Frame 051224/0125 →
Priority Claims (1)
JP JP2018-176151 · Sep 20, 2018 · national
Continuity (1)
Related Publication 20200099815A1 · Mar 26, 2020