IP Library Granted Patent US 11,418,749
Granted Patent B2
US 11,418,749 · App. 16/647,048 · Granted Aug 16, 2022

Solid-state image pick-up device and electronic device

Inventors: Takashi Moue (Kanagawa, JP); Yosuke Ueno (Kanagawa, JP); Tomonori Yamashita (Kanagawa, JP); Kazunori Hasebe (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N5/378H01L27/14603H01L27/14609H04N5/374
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Quick Facts
Patent No.
US 11,418,749
App. No.
16/647,048
Granted
Aug 16, 2022
Kind
B2
Abstract

A solid-state image pick-up device of the present disclosure includes a pixel array unit obtained by disposing a plurality of unit pixels, each of which includes a photoelectric conversion unit, in a matrix form, an amplifier unit that adjusts a level of a pixel signal output from a unit pixel through a vertical signal line provided to correspond to column arrangement of the pixel array unit, a sample and hold unit that samples and holds a pixel signal passing through the amplifier unit, and an analog-digital conversion unit that converts the pixel signal output from the sample and hold unit into a digital signal. Further, the sample and hold unit includes at least three capacitors that hold pixel signals and performs fetching of a pixel signal to one capacitor and outputting of an image signal fetched to another capacitor in advance to the analog-digital conversion unit in parallel.

Claims (68)

1. A solid-state image pick-up device, comprising:

an analog-digital conversion unit;

a pixel array unit that includes a plurality of unit pixels in a matrix, wherein

each unit pixel of the plurality of unit pixels includes a photoelectric conversion unit,

the plurality of unit pixels includes a unit pixel configured to output a pixel signal of a plurality of pixel signals through a vertical signal line, and

the vertical signal line corresponds to a column arrangement of the pixel array unit;

an amplifier unit that includes:

an inverting amplifier configured to output a voltage based on the pixel signal;

a plurality of level determination circuits, wherein each level determination circuit of the plurality of level determination circuits is configured to determine a level of the pixel signal based on the output voltage; and

a first output terminal,

wherein the amplifier unit is configured to:

adjust the level of the pixel signal based on the determination of the level of the pixel signal;

output, via the first output terminal, the pixel signal based on the adjustment of the level of the pixel signal; and

a sample and hold unit that includes:

at least three capacitors configured to hold the plurality of pixel signals;

a second output terminal different from the first output terminal; and

a reset switch configured to reset a potential of the second output terminal in the sample and hold unit, wherein

the sample and hold unit is configured to:

receive the pixel signal from the amplifier unit;

sample and hold the received pixel signal;

fetch the received pixel signal to a first capacitor of the at least three capacitors; and

output, via the second output terminal, an image signal fetched to a second capacitor of the at least three capacitors to the analog-digital conversion unit, wherein the received pixel signal is fetched in parallel with the output of the image signal, and

the analog-digital conversion unit is configured to convert, into a digital signal, the image signal output from the second output terminal of the sample and hold unit.

2. The solid-state image pick-up device according to claim 1 , further comprising a stacked structure that includes a first semiconductor substrate and a second semiconductor substrate, wherein

the pixel array unit is on the first semiconductor substrate, and

the sample and hold unit is on the second semiconductor substrate.

3. The solid-state image pick-up device according to claim 1 , wherein

the pixel signal includes:

a first reset signal output from the unit pixel during a reset operation, and

a first data signal output from the unit pixel during photoelectric conversion, and

the sample and hold unit further includes four capacitors with respect to a first pixel signal of the plurality of pixel signals and a second pixel signal of the plurality of pixel signals,

the unit pixel is further configured to output the first pixel signal at a first time and the second pixel signal at a second time subsequent to the first time,

first two capacitors of the four capacitors correspond to the first reset signal and the first data signal of the pixel signal, and

second two capacitors of the four capacitors correspond to a second reset signal and a second data signal of the image signal.

4. The solid-state image pick-up device according to claim 1 , wherein the amplifier unit further includes an adaptive gain type amplifier configured to adaptively adjust gain to obtain a constant signal level.

5. The solid-state image pick-up device according to claim 4 , wherein the amplifier unit is further configured to switch between at least two types of the gain.

6. The solid-state image pick-up device according to claim 5 , wherein the plurality of level determination circuits is configured to

switch between the at least two types of the gain based on the determination of the level.

7. The solid-state image pick-up device according to claim 6 , further comprising a digital signal processing unit, wherein

the analog-digital conversion unit is further configured to output the digital signal, and

the digital signal processing unit is configured to:

process the digital signal output from the analog-digital conversion unit; and

execute level adjustment on the digital signal based on the determination of the level.

8. The solid-state image pick-up device according to claim 7 , wherein the digital signal processing unit is further configured to execute compression processing on the digital signal based on the determination of the level.

9. An electronic device, comprising:

a solid-state image pick-up device including:

an analog-digital conversion unit;

a pixel array unit that includes a plurality of unit pixels in a matrix, wherein

each unit pixel of the plurality of unit pixels includes a photoelectric conversion unit,

the plurality of unit pixels includes a unit pixel configured to output a pixel signal of a plurality of pixel signals through a vertical signal line, and

the vertical signal line corresponds to a column arrangement of the pixel array unit;

an amplifier unit that includes:

an inverting amplifier configured to output a voltage based on the pixel signal;

a plurality of level determination circuits, wherein each level determination circuit of the plurality of level determination circuits is configured to determine a level of the pixel signal based on the output voltage; and

a first output terminal,

wherein the amplifier unit is configured to:

adjust the level of the pixel signal based on the determination of the level of the pixel signal; and

output, via the first output terminal, the pixel signal based on the adjustment of the level of the pixel signal; and

a sample and hold unit that includes:

at least three capacitors configured to hold the plurality of pixel signals;

a second output terminal different from the first output terminal; and

a reset switch configured to reset a potential of the second output terminal in the sample and hold unit, wherein

the sample and hold unit is configured to:

 receive the pixel signal from the amplifier unit;

 sample and hold the received pixel signal;

 fetch the received pixel signal to a first capacitor of the at least three capacitors; and

 output, via the second output terminal, an image signal fetched to a second capacitor of the at least three capacitors to the analog-digital conversion unit, wherein the received pixel signal is fetched in parallel with the output of the image signal, and

the analog-digital conversion unit is configured to convert, into a digital signal, the image signal output from the second output terminal of the sample and hold unit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2020
From: MOUE, TAKASHI; UENO, YOSUKE; YAMASHITA, TOMONORI; HASEBE, KAZUNORI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 052874/0100 →
Priority Claims (1)
JP 2017-182192 · Sep 22, 2017 · national
Continuity (1)
Related Publication 20200260034A1 · Aug 13, 2020
Cited By (1)
US 12,538,050