Host controller interface for universal serial bus (USB) power delivery
An apparatus, comprising a system management bus configured to communicate with a USB PDC, and a processor coupled to the system management bus and configured to send a power delivery configuration to the PDC, wherein the power delivery configuration comprises voltage and current settings, and receive a power delivery status from the PDC. Also disclosed is an apparatus comprising a power bus interface configured to communicate with a USB port partner, a system management bus interface configured to communicate with a host, and a processor coupled to the power bus interface and the system management bus interface, wherein the processor is configured to receive, via the system management bus interface, a power delivery configuration from the host, generate a power capability message based on the power delivery configuration, and send, via the power bus interface, the power capability message to the USB port partner.
1. A power delivery system comprising:
a power delivery controller (PDC) having a bus input_configured to receive a reset command from a host device, and an output port configured to send a hard reset signal to a powered device (PD) external to the power delivery system based on the reset command;
wherein the PDC is coupled to the host device via a system management bus including a SMBus; and
wherein when a reset command is received, the hard reset signal causes a bus voltage to be between approximately 0 volts and 0.5 volts for a first period then returning to between approximately 4.75 volts and 5.25 volts.
2. The power delivery system of claim 1 , further comprising a host controller.
3. The power delivery system of claim 2 , wherein the host controller is integrated with the PDC to form a single device.
4. The power delivery system of claim 1 , wherein the reset command to the PDC includes a one-bit hard reset field.
5. The power delivery system of claim 1 , wherein the PDC is configured to notify the host controller after sending the hard reset signal.
6. The power delivery system of claim 1 , wherein the PDC is configured to establish a Universal Serial Bus connection with the powered device.
7. The power delivery system of claim 5 , wherein the PDC is configured to generate the hard reset signal based on the reset command.
8. A Universal Serial Bus (USB) power delivery system comprising:
a USB power delivery controller (PDC) having a bus input configured to receive a reset command from a host device, and an output port configured to send a hard reset signal to a powered device (PD) external to the power delivery system based on the reset command;
wherein the PDC is coupled to the host device via a system management bus including a SMBus; and
wherein when a reset command is received, the hard reset signal causes a bus voltage to be between approximately 0 volts and 0.5 volts for a first period then returning to between approximately 4.75 volts and 5.25 volts.
9. The USB power delivery system of claim 8 , wherein the reset command to the USB PDC includes a one-bit hard reset field.
10. The USB power delivery system of claim 9 , wherein the USB PDC is configured to notify the host controller after sending the hard reset signal.
11. The USB power delivery system of claim 8 , wherein the USB PDC is configured to establish a Universal Serial Bus connection with the powered device.
12. The power delivery system of claim 8 , wherein the USB PDC is configured to generate the hard reset signal based on the reset command.
13. An integrated circuit comprising:
a USB power device controller (PDC) having a bus input configured to receive a reset command from a host device, a processor configured to generate a hard reset signal based on the reset command, and an output port configured to transmit the hard reset signal to a USB powered device (PD) external to a power delivery system including the integrated circuit;
wherein the PDC is coupled to the host device via a system management bus including a SMBus; and
wherein when a reset command is received, the hard reset signal causes a bus voltage to be between approximately 0 volts and 0.5 volts for a first period then returning to between approximately 4.75 volts and 5.25 volts.
14. The integrated circuit of claim 13 , wherein the USB PDC is configured to send the hard reset signal to the USB PD.
15. The integrated circuit of claim 13 , wherein USB PDC is configured to notify the host controller after sending the hard reset signal.