Real time output control based on machine learning hardware implementation
A machine learning system that includes three machine learning models implemented in a hardware processor, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the three machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module is implemented in hardware and receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.
1. A machine learning system configured to provide an output based on one or more inputs, the machine learning system comprising:
three machine learning models, each configured to:
receive:
the one or more inputs; and
an additional feature input based on the one or more inputs; and
produce a machine learning model output;
wherein each of the three machine learning models is implemented in a hardware processor;
a first-level feature creation module, configured to:
receive the one or more inputs;
perform a feature creation operation on the one or more inputs;
create the additional feature inputs; and
provide the additional feature inputs to each of the three machine learning models;
wherein:
the first-level feature creation operation filters one or more aspects of the one or more inputs; and
the first-level feature creation operation is implemented in hardware; and
a combination module, configured to:
receive each of the three machine learning model outputs; and
produce a machine learning system output.
2. The machine learning system of claim 1 , wherein the feature creation operation comprises one or more of: calculating a slew rate, calculating an average value, calculating a differential input value, performing filtering, and performing a transfer function.
3. The machine learning system of claim 1 , further comprising one or more second-level feature creation module, each configured to:
receive at least one of the three machine learning model outputs;
perform a feature creation operation on the one or more system inputs;
create second-level additional feature outputs; and
provide the second-level additional feature outputs to the combination module;
wherein:
the second-level feature creation operation filters one or more aspects of at least one of the three machine learning model outputs; and
the second-level feature creation operation is implemented in hardware.
4. The machine learning system of claim 3 , wherein the second-level feature creation operation comprises one or more of: calculating a slew rate, calculating an average value, calculating a differential input value, performing filtering, and performing a transfer function.
5. The machine learning system of claim 1 , wherein:
the combination module is a machine learning model; and
the combination module performs a machine language calculation on the one or more machine learning model outputs.
6. The machine learning system of claim 1 , wherein:
the three machine learning models define a first machine learning model, a second machine learning model, and a third machine learning model;
the first machine learning model is a multi-layer perception (MLP) machine learning model;
the second machine learning model is a support vector regression (SVR) machine learning model; and
the third machine learning model is a linear regression machine learning model.
7. The machine learning system of claim 1 , wherein the hardware processor is a field programmable gate array (FPGA) or in an application specific integrated circuit (ASIC).
8. The machine learning system of claim 7 , wherein the first-level feature creation module is implemented in a FPGA or in an ASIC.
9. The machine learning system of claim 3 , wherein the one or more second-level feature creation modules are implemented in a FPGA or in an ASIC.
10. The machine learning system of claim 1 , further comprising a fourth machine learning model.
11. A method of using a machine learning system to provide an output based on one or more inputs, the machine learning system comprising three machine learning models each implemented in a hardware processor, a first-level feature creation module, and a combination module, the method comprising:
receiving, by a first-level feature creation module, one or more inputs;
performing, by the first-level feature creation module, a feature creation operation on the one or more inputs;
wherein the first-level feature creation operation performs a calculation on one or more aspects of the one or more inputs;
calculating, by the first-level feature creation module, additional feature outputs;
providing, from the first-level feature creation module, the additional feature outputs to at least one of the one or machine learning models;
receiving, by each of the one or more machine learning models:
the one or more inputs; and
the additional feature outputs; and
receiving, by the combination module, the one or more machine learning model outputs; and
producing, by the combination module, a machine learning channel output.
12. The method of claim 11 , wherein the feature creation operation comprises one or more of: calculating a slew rate, calculating an average value, calculating a differential input value, performing filtering, and performing a transfer function.
13. The method of claim 11 , wherein the machine learning channel further comprises one or more second-level feature creation module, each configured to:
receive at least one of the three machine learning model outputs;
perform a feature creation operation on the one or more inputs;
create second-level additional feature outputs; and
provide the second-level additional feature outputs to the combination module;
wherein:
the second-level feature creation operation filters one or more aspects of at least one of the three machine learning model outputs; and
the second-level feature creation operation is implemented in hardware.
14. The method of claim 13 , wherein the second-level feature creation operation comprises one or more of: calculating a slew rate, calculating an average value, calculating a differential input value, performing filtering, and performing a transfer function.
15. The method of claim 11 , wherein:
the combination module is a machine learning model; and
the combination module performs a machine language calculation on the one or more machine learning model outputs.
16. The method of claim 11 , wherein:
the three machine learning models define a first machine learning model, a second machine learning model, and a third machine learning model;
the first machine learning model is a multi-layer perception (MLP) machine learning model;
the second machine learning model is a support vector regression (SVR) machine learning model; and
the third machine learning model is a linear regression machine learning model.
17. The method of claim 11 , wherein the hardware processor is a field programmable gate array (FPGA) or in an application specific integrated circuit (ASIC).
18. The method of claim 11 , wherein the first-level feature creation module is implemented in a FPGA or in an ASIC.
19. The method of claim 13 , wherein the one or more second-level feature creation modules are implemented in a FPGA or in an ASIC.
20. The method of claim 11 , wherein the machine learning system further comprises a fourth machine learning model.