Speculative execution of correlated memory access instruction methods, apparatuses and systems

1. A processor core, comprising:

an instruction fetch unit, wherein the instruction fetch unit comprises a speculative execution predictor adapted to: compare a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and mark the memory access instruction based on the comparison, wherein the memory access instruction is a load instruction or a store instruction, and wherein the table entry comprises program counters of a load instruction and a store instruction that have an address correlation;

a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions to an execution unit; and

the execution unit adapted to execute the marked memory access instructions according to the send order.

2. The processor core according to claim 1 , wherein the instruction fetch unit further comprises a register set adapted to store the table entry.

3. The processor core according to claim 1 , wherein the speculative execution predictor is further adapted to:

update a table entry in the speculative execution predictor according to a speculative execution prediction result of the memory access instruction.

4. The processor core according to claim 2 , wherein the register set further comprises a plurality of register groups, and wherein each register group comprises a saturation counter and one or two program counter (PC) registers adapted to store one table entry.

5. The processor core according to claim 4 , wherein the speculative execution predictor is further adapted to start speculative prediction when a value of the saturation counter is greater than a first given value and terminate the speculative prediction when the value of the saturation counter is less than a second given value, and wherein the first given value is greater than the second given value.

6. The processor core according to claim 5 , wherein, for one pair of a store instruction and a load instruction, the speculative execution predictor is further adapted to increase the value of the saturation counter according to a speculative prediction error before starting the speculative prediction and decrease the value of the saturation counter according to the speculative prediction error after starting the speculative prediction.

7. The processor core according to claim 1 , wherein the instruction fetch unit further comprises a pre-decoding unit adapted to distinguish a general instruction and the memory access instruction and send the general instruction to the scheduler unit and the memory access instruction to the speculative execution predictor.

8. The processor core according to claim 1 , wherein the speculative execution predictor only marks a load instruction that is expected to fail speculative execution.

9. The processor core according to claim 1 , wherein the speculative execution predictor only marks a store instruction that is expected to fail speculative execution.

10. The processor core according to claim 1 , wherein the scheduler unit is further adapted to send a marked load instruction after a marked store instruction is sent.

11. The processor core according to claim 10 , wherein the scheduler unit comprises an instruction send queue and a send blocking execution module, wherein:

the instruction send queue is used to buffer every instruction received; and

the send blocking execution module is adapted to block the marked load instruction and send the marked load instruction after the marked store instruction is sent.

12. The processor core according to claim 3 , further comprising a retirement unit, wherein the retirement unit comprises a prediction result summary module, wherein the prediction result summary module is adapted to summarize the speculative execution prediction result and provide the speculative execution prediction result of the memory access instruction to the speculative execution predictor.

13. A processor, comprising the processor core according to claim 1 .

14. A system-on-chip, comprising the processor core according to claim 1 .

15. An apparatus, comprising a memory coupled by using a bus, and the processor according to claim 13 .

16. An instruction processing method, comprising:

acquiring an instruction packet;

pre-decoding the instruction packet to distinguish a memory access instruction and a general instruction in the instruction packet, wherein the memory access instruction is a load instruction or a store instruction, and wherein the general instruction is an instruction other than the memory access instruction in an instruction set;

performing speculative prediction on a pair of memory access instructions in the instruction packet and marking the memory access instructions according to the speculative prediction;

adjusting a send order of the marked memory access instructions and sending the marked memory access instructions according to the send order; and

executing the memory access instructions according to the send order.

17. The instruction processing method according to claim 16 , wherein the adjusting the send order of the marked memory access instructions and sending the marked memory access instructions according to the send order comprises:

sending a marked load instruction after a marked store instruction is sent.