Display apparatus

1. A display apparatus comprising:

a pixel portion in which a plurality of pixels are arranged, each of the plurality of pixels being connected to a scan line and a data line;

a source output line to which a data signal is transmitted;

a data driver configured to transmit a data signal to the source output line;

a data distributer configured to selectively connect the source output line to n data lines, n being a positive integer greater than or equal to two; and

a latch portion arranged between the data distributer and the pixel portion,

wherein the latch portion includes a plurality of latches, each of the plurality of latches connected to a corresponding one of n−1 data lines excluding a data line, from among the n data lines, connected to the source output line by the data distributer, at a timing at which a scan signal is transmitted to the scan line.

2. The apparatus of claim 1 , wherein each of the plurality of latches includes:

an amplifier including an input terminal connected to the source output line and an output terminal connected to a corresponding data line from among the n−1 data lines; and

a capacitor connected between the input terminal and a power portion.

3. The apparatus of claim 2 , wherein the power portion applies a first power voltage and a second power voltage to each of the plurality of pixels.

4. The apparatus of claim 2 , wherein a first input terminal of the amplifier is connected to the source output line, and a second input terminal of the amplifier is connected to the output terminal.

5. The apparatus of claim 4 , wherein the latch further includes:

a first resistor between the second input terminal of the amplifier and the power portion; and a second resistor between the second input terminal and the output terminal.

6. The apparatus of claim 4 , wherein the latch portion further includes a first transistor connected between the first input terminal and the output terminal of the amplifier.

7. The apparatus of claim 6 , wherein the first transistor is turned on at a timing at which the corresponding data line is connected to the source output line.

8. The apparatus of claim 6 , wherein the latch portion further includes a second transistor connected between the first input terminal of the amplifier and the source output line.

9. The apparatus of claim 8 , wherein the first transistor is turned on at a timing at which the corresponding data line is connected to the source output line, and

the second transistor is turned on at a timing at which the scan signal is transmitted to the scan line.

10. The apparatus of claim 1 , wherein the pixels include red pixels, blue pixels, and green pixels, the red pixels being connected to a first data line on a first column, the blue pixels being connected to a second data line on a second column, and the green pixels being connected to a third data line on a third column, and

the latch portion includes a first latch and a second latch, the first latch being connected to the first data line, and the second latch being connected to the second data line.

11. The apparatus of claim 1 , wherein the pixels include red pixels, blue pixels, and green pixels, the red pixels being connected to a first data line on a first column, the blue pixels being connected to a second data line on a second column, and the green pixels being connected to a third data line on a third column, and

the latch portion includes a latch connected to the first data line.

12. The apparatus of claim 1 , wherein the data distributer includes a plurality of switches, and

each of the plurality of switches is connected between a corresponding data line from among the n data lines and the source output line.

13. A display apparatus comprising:

a plurality of pixels, each of the plurality of pixels connected to a scan line and a data line;

a source output line to which a data signal is transmitted;

a demultiplexer including a plurality of switches connected to the source output line and n data lines, n being a positive integer greater than or equal to two; and

a plurality of latches connected to switches turned off at a timing at which a scan signal is transmitted to the scan line, from among the plurality of switches and the n−1 data lines excluding a data line, from among the n data lines, connected to the source output line at the timing at which the scan signal is transmitted to the scan line.

14. The apparatus of claim 13 , wherein each of the plurality of latches includes:

an amplifier including an input terminal connected to the source output line and an output terminal connected to a corresponding data line from among the n data lines; and

a capacitor connected between the input terminal and a power portion, and

the power portion applies a first power voltage and a second power voltage to each of the plurality of pixels.

15. The apparatus of claim 14 , wherein a first input terminal of the amplifier is connected to the source output line, and a second input terminal of the amplifier is connected to the output terminal.

16. The apparatus of claim 15 , wherein the latch further includes a first resistor between the second input terminal of the amplifier and the power portion, and a second resistor between the second input terminal and the output terminal.

17. The apparatus of claim 15 , wherein the latch portion further includes a first transistor connected between the input terminal and the output terminal of the amplifier.

18. The apparatus of claim 17 , wherein the first transistor is turned on at a timing at which the corresponding data line is connected to the source output line.

19. The apparatus of claim 17 , wherein the latch portion further includes a second transistor connected between the first input terminal of the amplifier and the source output line.

20. The apparatus of claim 19 , wherein the first transistor is turned on at a timing at which the corresponding data line is connected to the source output line, and

the second transistor is turned on at a timing at which a scan signal is transmitted to the scan line.