In-situ formation of metal gate modulators
A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.
1. A method comprising:
forming a first gate dielectric on a first semiconductor region;
depositing a first work-function layer over the first gate dielectric;
depositing a first silicon layer over the first work-function layer, wherein at a time the first silicon layer is deposited, the first silicon layer comprises elemental silicon;
depositing a first glue layer over the first silicon layer, wherein the first work-function layer, the first silicon layer, and the first glue layer are in-situ deposited, and wherein during an entirety of in-situ deposition processes for depositing the first work-function layer, the first silicon layer, and the first glue layer, no oxygen (O 2 ) is used;
depositing a first filling-metal over the first glue layer; and
performing a planarization process, wherein remaining portions of the first glue layer, the first silicon layer, and the first work-function layer form portions of a gate electrode.
2. The method of claim 1 further comprising depositing a metal-containing capping layer over the first work-function layer, wherein the first silicon layer is further over the metal-containing capping layer, and wherein the first work-function layer, the metal-containing capping layer, the first silicon layer, and the first glue layer are in-situ performed.
3. The method of claim 1 , wherein the first silicon layer is formed by thermally soaking a wafer that comprises the first work-function layer in a silicon-based precursor.
4. The method of claim 1 further comprising:
forming a second gate dielectric on a second semiconductor region;
depositing a metal-containing layer over the second gate dielectric;
depositing a second work-function layer over the metal-containing layer, wherein the metal-containing layer and the second work-function layer are formed of different materials;
depositing a second silicon layer over the second work-function layer;
depositing a second glue layer over the second silicon layer, wherein the second work-function layer, the second silicon layer, and the second glue layer are in-situ performed; and
depositing a second filling-metal over the second glue layer.
5. The method of claim 4 , wherein the metal-containing layer and the second work-function layer are ex-situ performed, with a vacuum break there between.
6. The method of claim 1 , wherein the first glue layer has a thickness smaller than 25 Å.
7. An integrated circuit device comprising:
a semiconductor region;
a gate dielectric over the semiconductor region;
a work-function layer over the gate dielectric;
a silicon layer over the work-function layer, wherein the silicon layer is an electrically conductive layer;
a glue layer over and contacting the silicon layer, and wherein an interface between the silicon layer and the glue layer is free from oxygen; and
a filling-metal region over and contacting the glue layer.
8. The integrated circuit device of claim 7 , wherein the glue layer has a thickness smaller than 25 Å.
9. The integrated circuit device of claim 7 , wherein the silicon layer comprises elemental silicon atoms.
10. The integrated circuit device of claim 7 , wherein the glue layer comprises titanium nitride.
11. The integrated circuit device of claim 7 further comprising a titanium nitride layer between the work-function layer and the silicon layer.
12. The integrated circuit device of claim 7 , wherein the work-function layer is an n-work-function layer.
13. The integrated circuit device of claim 7 , wherein the silicon layer has a thickness smaller than about 10 Å.
14. The integrated circuit device of claim 7 , wherein the silicon layer is free from silicon oxide therein.
15. The integrated circuit device of claim 7 , wherein the glue layer comprises titanium nitride.
16. A device comprising:
a semiconductor fin;
a high-k dielectric on the semiconductor fin;
a work-function layer over the high-k dielectric;
a first titanium nitride layer over the work-function layer;
a silicon layer over the first titanium nitride layer;
a second titanium nitride layer over the silicon layer, wherein an interface between the silicon layer and the second titanium nitride layer is free from oxygen, wherein the silicon layer is configured to electrically interconnect the first titanium nitride layer and the second titanium nitride layer; and
a filling-metal region over and contacting the second titanium nitride layer.
17. The device of claim 16 , wherein the first titanium nitride layer is in physical contact with the work-function layer.
18. The device of claim 16 , wherein the silicon layer comprises elemental silicon.
19. The device of claim 16 , wherein the silicon layer has a thickness smaller than about 10 Å.
20. The device of claim 16 , wherein the silicon layer is free from silicon oxide therein.