Trench isolation with conductive structures
The present disclosure describes a semiconductor device having metal boundary trench isolation with electrically conductive intermediate structures acting as a metal diffusion barrier. The semiconductor structure includes a first fin structure and a second fin structure on a substrate, an insulating layer between the first and second fin structures, a gate dielectric layer on the insulating layer and the first and second fin structures, and a first work function stack and a second work function stack on the gate dielectric layer. The first work function stack is over the first fin structure and a first portion of the insulating layer, and the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion. The semiconductor structure further includes a conductive intermediate structure on the gate dielectric layer and between the first and second work function stacks.
1. A semiconductor structure, comprising:
a first fin structure and a second fin structure on a substrate;
an insulating layer between the first and second fin structures;
a gate dielectric layer on the insulating layer and the first and second fin structures;
a first work function stack on the gate dielectric layer, wherein the first work function stack is over the first fin structure and a first portion of the insulating layer;
a second work function stack on the gate dielectric layer, wherein the second work function stack is over the second fin structure and a second portion of the insulating layer adjacent to the first portion; and
a conductive structure in contact with the gate dielectric layer and between the first and second work function stacks.
2. The semiconductor structure of claim 1 , wherein a first portion of the gate dielectric layer comprises an interfacial layer on the first and second fin structures and a high-k dielectric layer on the interfacial layer, and wherein a second portion of the gate dielectric layer comprises the high-k dielectric layer on the insulating layer.
3. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises an interfacial layer on the insulating layer and the first and second fin structures and comprises a high-k dielectric layer on the interfacial layer.
4. The semiconductor structure of claim 2 , wherein a portion of the conductive structure is in the gate dielectric layer.
5. The semiconductor structure of claim 1 , wherein the conductive structure is in contact with sidewalk of the first and second work function stacks.
6. The semiconductor structure of claim 1 , wherein:
the first work function stack comprises an aluminum-free work function layer,
the second work function stack comprises an aluminum-based work function layer, and
the conductive structure separates the aluminum-free work function layer and the aluminum-based work function layer.
7. The semiconductor structure of claim 1 , wherein the conductive structure comprises at least one of a capping layer, a glue layer, a work function metal layer, and a metal fill layer.
8. The semiconductor structure of claim 7 , wherein the capping layer comprises silicon or silicon-titanium, and wherein the glue layer comprises titanium, titanium nitride, titanium silicon nitride, or cobalt.
9. A semiconductor device, comprising:
a first transistor comprising a first work function stack;
a second transistor comprising a second work function stack;
an insulating layer between the first and second transistors;
a gate dielectric layer between the insulating layer and the first work function stack and between the insulating layer and the second work function stack; and
a conductive structure in contact with the gate dielectric layer and between the first and second work function stacks.
10. The semiconductor device of claim 9 , wherein the gate dielectric layer comprises a high-k dielectric layer on the insulating layer.
11. The semiconductor device of claim 10 , wherein the gate dielectric layer comprises an interfacial layer on the insulating layer and a high-k dielectric layer on the interfacial layer.
12. The semiconductor device of claim 10 , wherein a portion of the barrier structure is in the gate dielectric layer.
13. The semiconductor device of claim 9 , wherein the barrier structure is in contact with the first and second work function stacks.
14. The semiconductor device of claim 9 , wherein:
the first work function stack comprises an aluminum-free work function layer,
the second work function stack comprises an aluminum-based work function layer, and
the barrier structure separates the aluminum-free work function layer and the aluminum-based work function layer.
15. The semiconductor device of claim 9 , wherein the barrier structure comprises at least one of a capping layer, a glue layer, a work function metal layer, and a metal fill layer.
16. The semiconductor device of claim 15 , wherein the capping layer comprises silicon or silicon-titanium, and wherein the glue layer comprises titanium, titanium nitride, titanium silicon nitride, or cobalt.
17. A method, comprising:
forming a gate dielectric layer on a first fin structure, a second fin structure, and an insulating layer between the first and second fin structures;
forming a first work function stack and a second work function stack on the gate dielectric layer and over the first fin structure and the second fin structure, respectively;
forming a trench between the first and second work function stacks, wherein the trench exposes top surfaces of the gate dielectric laver; and
forming a conductive structure on the gate dielectric layer in the trench.
18. The method of claim 17 , wherein forming the trench comprises etching a first portion of the first work function stack and a second portion of the second work function stack, wherein the first portion is adjacent to the second portion.
19. The method of claim 17 , wherein forming the trench comprises:
etching a first portion of the first work function stack and a second portion of the second work function stack, wherein the first portion is adjacent to the second portion; and
etching a portion of the gate dielectric layer below the first and second portions.
20. The method of claim 17 , wherein forming the conductive structure comprises depositing at least one of a capping layer, a glue layer, a work function metal layer, and a metal fill layer in the trench.