Buried etch-stop layer to help control transistor source/drain depth
Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.
1. An integrated circuit including at least one transistor, the integrated circuit comprising:
a substrate;
a body above the substrate, the body including semiconductor material, and the body having a lateral width;
a gate electrode at least above the body, the gate electrode including one or more metals;
a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics;
a source region and a drain region, the body between the source and drain regions, the source and drain regions including a semiconductor material that is compositionally different from the semiconductor material of the body; and
a layer between the substrate and the body, the layer between the substrate and the source region, the layer between the substrate and the drain region, the layer being continuous from between the substrate and the source region to between the substrate and the drain region, the layer including semiconductor material that is compositionally different from the semiconductor material included in the body and compositionally different from the semiconductor material of the source region and the drain region, wherein the layer is in contact with the semiconductor material of the source region and the drain region, and wherein the layer does not extend layerally beyond the lateral width of the body.
2. The integrated circuit of claim 1 , wherein the substrate is a bulk silicon substrate.
3. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes germanium.
4. The integrated circuit of claim 3 , wherein the semiconductor material included in the body further includes silicon.
5. The integrated circuit of claim 3 , wherein the semiconductor material included in the layer includes silicon.
6. The integrated circuit of claim 1 , wherein the semiconductor material included in the body includes group III-V semiconductor material.
7. The integrated circuit of claim 6 , wherein the group III-V semiconductor material included in the body includes arsenic.
8. The integrated circuit of claim 6 , wherein the group III-V semiconductor material included in the body includes phosphorous.
9. The integrated circuit of claim 1 , wherein the layer includes a thickness between the substrate and the body of 1 to 20 nanometers.
10. The integrated circuit of claim 1 , wherein the layer is relatively thicker between the substrate and the body than between the substrate and the source region.
11. The integrated circuit of claim 1 , wherein, for a given etchant, the semiconductor material included in the body has a higher etch rate than an etch rate for the semiconductor material included in the layer.
12. The integrated circuit of claim 1 , wherein the body is a fin, the fin between two portions of the gate electrode.
13. The integrated circuit of claim 12 , wherein the fin has a height of at least 20 nanometers between the two portions of the gate electrode.
14. The integrated circuit of claim 1 , wherein the gate electrode wraps around the body.
15. The integrated circuit of claim 14 , wherein the body is a nanowire or a nanoribbon.
16. A computing system comprising the integrated circuit of claim 1 .
17. An integrated circuit including at least one transistor, the integrated circuit comprising:
a substrate, the substrate being a bulk silicon substrate;
a body above the substrate, the body including semiconductor material, and the body having a lateral width;
a gate electrode at least above the body, the gate electrode including one or more metals;
a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics;
a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material and dopant;
a first layer between the substrate and the body, the first layer between the substrate and the source region, the first layer between the substrate and the drain region, the first layer being continuous from between the substrate and the source region to between the substrate and the drain region, the first layer including the semiconductor material that is included in the body; and
a second layer between the first layer and the body, the second layer between the first layer and the source region, the second layer between the first layer and the drain region, the second layer being continuous from between the first layer and the source region to between the first layer and the drain region, the second layer being relatively thicker between the first layer and the body than between the first layer and the source region, the second layer including semiconductor material that is compositionally different from the semiconductor material included in the body, wherein the second layer does not extend layerally beyond the lateral width of the body.
18. The integrated circuit of claim 17 , wherein the semiconductor material included in the body and the first layer includes germanium, and the semiconductor material included in the second layer includes silicon.
19. A method of forming an integrated circuit including at least one transistor, the method comprising:
providing a substrate;
forming a body above the substrate, the body including semiconductor material, the body having a lateral width;
forming a gate structure at least above the body, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the body, the gate electrode including one or more metals, the gate dielectric including one or more dielectrics;
forming a source region and a drain region, the body between the source and drain regions, the source and drain regions including a semiconductor material that is compositionally different from the semiconductor material of the body; and
forming a layer between the substrate and the body, the layer between the substrate and the source region, the layer between the substrate and the drain region, the layer being continuous from between the substrate and the source region to between the substrate and the drain region, the layer including semiconductor material that is compositionally different from the semiconductor material included in the body and compositionally different from the semiconductor material of the source region and the drain region, wherein the layer is in contact with the semiconductor material of the source region and the drain region, and wherein the layer does not extend layerally beyond the lateral width of the body.
20. The method of claim 19 , wherein the source and drain regions are formed prior to forming the gate structure.