Junctionless field-effect transistor having metal-interlayer-semiconductor structure and manufacturing method thereof
View Patent ↗A semiconductor component is disclosed. The semiconductor component can include: a semiconductor layer injected with a same type of dopant; a gate electrode formed above the semiconductor layer with a gate insulation film positioned in-between; a dielectric layer formed on the semiconductor layer at both sides of the gate electrode; and source/drain electrodes each formed on the dielectric layer.
1. A junctionless field-effect transistor comprising:
a semiconductor layer injected with a same type of dopant;
a gate electrode disposed on a gate insulation film disposed on the semiconductor layer;
a dielectric layer disposed on the semiconductor layer at both sides of the gate electrode; and
source/drain electrodes each disposed on the dielectric layer,
wherein the dielectric layer is a metal oxide and has a thickness of 2 nm to 4 nm, and the semiconductor layer is an n-type semiconductor, and the dielectric layer is doped with an n-type material.
2. The junctionless field-effect transistor of claim 1 , wherein the dielectric layer is formed by an ALD (atomic layer deposition) process.
3. The junctionless field-effect transistor of claim 1 , wherein the dielectric has a thickness of 2.4 nm.
4. The junctionless field-effect transistor of claim 1 , wherein the dielectric layer comprises any one of lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), magnesium oxide (MgO), germanium oxide (GeO 2 ), and lutetium oxide (Lu 2 O 3 ).
5. A junctionless field-effect transistor comprising:
a semiconductor layer injected with a same type of dopant;
a gate electrode disposed on a gate insulation film disposed on the semiconductor layer;
a dielectric layer disposed on the semiconductor layer at both sides of the gate electrode; and
source/drain electrodes each disposed on the dielectric layer,
wherein the dielectric layer is a metal oxide and has a thickness of 2 nm to 4 nm, and
the source/drain electrodes comprise any one of tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (HfN), and tungsten nitride (WN).
6. A manufacturing method for a junctionless field-effect transistor, the manufacturing method comprising:
forming a gate structure on a semiconductor layer, the semiconductor layer injected with an n-type dopant;
forming a dielectric layer doped with an n-type material on the semiconductor layer on both sides of the gate structure; and
forming source/drain electrodes on the dielectric layer,
wherein the dielectric layer is a metal oxide and has a thickness of 2 nm to 4 nm, and the dielectric layer comprises zinc oxide (ZnO).
7. The manufacturing method of claim 6 , wherein the gate structure comprises:
a gate electrode; and
a gate insulation film formed between the gate electrode and the semiconductor layer.
8. The manufacturing method of claim 6 , wherein the forming of the dielectric layer comprises forming the dielectric layer by way of an ALD (atomic layer deposition) process.
9. The manufacturing method of claim 6 , wherein the dielectric layer comprises any one of lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), magnesium oxide (MgO), germanium oxide (GeO 2 ), and lutetium oxide (Lu 2 O 3 ).
10. A semiconductor component comprising:
a semiconductor layer injected with a same type of dopant;
a gate electrode disposed on a gate insulation film disposed on the semiconductor layer;
a dielectric layer disposed on the semiconductor layer at both sides of the gate electrode; and
source/drain electrodes each disposed on the dielectric layer,
wherein the dielectric layer comprises any one of lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), magnesium oxide (MgO), germanium oxide (GeO 2 ), and lutetium oxide (Lu 2 O 3 ), and
the semiconductor layer is an n-type semiconductor, and the dielectric layer is doped with an n-type material.
11. The semiconductor component of claim 10 , wherein the dielectric layer is formed by an ALD (atomic layer deposition) process.
12. The semiconductor component of claim 10 , wherein the dielectric layer further comprises hafnium dioxide (HfO 2 ).
13. The semiconductor component of claim 10 , wherein the dielectric has a thickness of 2 nm to 4 nm.
14. The semiconductor component of claim 10 , wherein the dielectric has a thickness of 2.4 nm.
15. A semiconductor component comprising:
a semiconductor layer injected with a same type of dopant;
a gate electrode disposed on a gate insulation film disposed on the semiconductor layer;
a dielectric layer disposed on the semiconductor layer at both sides of the gate electrode; and
source/drain electrodes each disposed on the dielectric layer,
wherein the dielectric layer comprises any one of lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), magnesium oxide (MgO), germanium oxide (GeO 2 ), and lutetium oxide (Lu 2 O 3 ), and
the source/drain electrodes comprise any one of tantalum nitride (TaN), titanium nitride (TiN), hafnium nitride (HfN), and tungsten nitride (WN).
16. A junctionless field-effect transistor comprising:
a semiconductor layer injected with an n-type dopant;
a gate electrode disposed on a gate insulation film disposed on the semiconductor layer;
a dielectric layer doped with an n-type material, and disposed on the semiconductor layer at both sides of the gate electrode; and
source/drain electrodes each disposed on the dielectric layer,
wherein the dielectric layer is a metal oxide and has a thickness of 2 nm to 4 nm, and the dielectric layer comprises zinc oxide (ZnO).