Gate all around structure with additional silicon layer and method for forming the same

1. A method for manufacturing a semiconductor structure, comprising:

forming nanowire structures over a substrate;

forming a gate structure across nanowire structures;

forming a source/drain structure adjacent to the gate structure;

forming a Si layer over the source/drain structure;

forming a SiGe layer over the Si layer;

oxidizing the SiGe layer to form an oxide layer; and

forming a contact through the Si layer over the source/drain structure.

2. The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:

forming a gate spacer on a sidewall of the gate structure,

wherein the Si layer is sandwiched between the contact and the gate spacer and is in direct contact with the contact and the gate spacer.

3. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein a concentration of Ge in the SiGe layer is in a range of about 20% to about 70%.

4. The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:

removing the oxide layer;

forming an etch stop layer over the Si layer after the oxide layer is removed; and

forming an interlayer dielectric layer over the etch stop layer,

wherein the contact is formed through the interlayer dielectric layer.

5. The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:

alternately stacking first semiconductor material layers and second semiconductor layers over the substrate;

patterning the first semiconductor material layers and the second semiconductor layers to form a fin structure;

recessing the fin structure to form a recess, wherein the source/drain structure is formed in the recess;

removing the gate structure to form an opening;

removing the second semiconductor layers under the opening to form the nanowire structures; and

forming a metal gate structure surrounding the nanowire structures.

6. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein the SiGe layer is thicker than the Si layer.

7. The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:

diffusing the Ge in the SiGe layer to an interface between the Si layer and SiGe layer to form a high Ge layer.

8. A method for manufacturing a semiconductor structure, comprising:

alternately stacking first semiconductor material layers and second semiconductor layers over a substrate;

patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure in a first region of the substrate and a second fin structure in a second region of the substrate;

forming a gate structure across the first fin structure and the second fin structure;

recessing the first fin structure and the second fin structure to form a first recess in the first region and a second recess in the second region;

forming a mask layer covering the second recess and the gate structure in the second region;

forming a first source/drain structure in the first recess;

forming a Si layer over the first source/drain structure;

removing the mask layer;

forming an oxide layer over the Si layer; and

forming a second source/drain structure in the second recess.

9. The method for manufacturing the semiconductor structure as claimed in claim 8 , wherein forming the oxide layer over the Si layer further comprises:

forming a SiGe layer over the Si layer; and

oxidizing the SiGe layer.

10. The method for manufacturing the semiconductor structure as claimed in claim 9 , wherein the SiGe layer is formed before removing the mask layer, and the SiGe layer is oxidized after removing the mask layer.

11. The method for manufacturing the semiconductor structure as claimed in claim 9 , wherein the SiGe layer is formed and oxidized before removing the mask layer.

12. The method for manufacturing the semiconductor structure as claimed in claim 8 , further comprising:

removing the oxide layer after forming the second source/drain structure in the second recess.

13. The method for manufacturing the semiconductor structure as claimed in claim 12 , further comprising:

forming an etch stop layer over the Si layer in the first region and over the second source/drain structure in the second region;

forming an interlayer dielectric layer over the etch stop layer; and

forming a first contact through the interlayer dielectric layer and the Si layer over the first source/drain structure.

14. The method for manufacturing the semiconductor structure as claimed in claim 12 , wherein removing the oxide layer further comprises:

thinning the oxide layer before forming the second source/drain structure; and

etching a remnant of the oxide layer after forming the second source/drain structure.

15. A semiconductor structure, comprising:

a substrate;

nanowire structures formed over the substrate;

a gate structure formed around the nanowire structure;

a gate spacer formed on a sidewall of the gate structure;

a source/drain structure formed adjacent to the gate structure;

a contact formed over the source/drain structure; and

a Si layer sandwiched between the gate spacer and the contact,

wherein a top surface of the Si layer is lower than a top surface of the gate spacer.

16. The semiconductor structure as claimed in claim 15 , further comprising:

an oxide layer formed over the Si layer; and

an etch stop layer formed over the oxide layer,

wherein the oxide layer and the etch stop layer are in direct contact with the gate spacer and the contact.

17. The semiconductor structure as claimed in claim 15 , further comprising:

a SiGe layer formed over the Si layer;

an oxide layer formed over the SiGe layer; and

an etch stop layer formed over the oxide layer,

wherein the SiGe layer, the oxide layer, and the etch stop layer are sandwiched between the gate spacer and the contact.

18. The semiconductor structure as claimed in claim 15 , further comprising:

inner spacers formed between the gate structure and the source/drain structure,

wherein a bottom surface of the Si layer is higher than top surfaces of the inner spacers.

19. The semiconductor structure as claimed in claim 15 , further comprising:

a silicide layer formed over the source/drain structure,

wherein a top surface of the silicide layer is lower than a top surface of the Si layer.

20. The semiconductor structure as claimed in claim 15 , further comprising:

a contact etch stop layer formed over the Si layer,

wherein the contact etch stop layer and the Si layer are in direct contact with a sidewall of the gate spacer.