Voltage regulator with multi-level, multi-phase buck architecture
A voltage regulator having a multi-level, multi-phase architecture is disclosed. The circuit includes a two-level buck converter and an N-level buck converter each coupled to an output node, wherein N is an integer value of three or more. During operation, the two-level buck converter provides one of two possible voltages to a first inductor. The N-level buck converter provides, during operation, one of N voltages to a second inductor. The first and second inductors each convert respectively received voltages to currents, which are provided to a common output node. A control circuit controls the activation of transistors in each of the two-level and N-level buck converters in such a manner as to cause the voltage on the output node to be maintained at a desired level.
1. A circuit comprising:
a first two-level buck converter configured to generate one of two voltage levels, the first two-level buck converter including a first inductor coupled to receive one of the two voltage levels and configured to provide a corresponding first current on an output node;
a first N-level buck converter configured to generate one of N voltage levels, wherein N is an integer value of three or more, and wherein the first N-level buck converter includes a second inductor coupled to receive one of the N voltage levels and configured to provide a corresponding second current on the output node;
at least one M-level buck converter configured to provide a corresponding current to the output node, wherein M is an integer value of three or more and wherein M is different than N, wherein the at least one M-level buck converter is configured to provide a corresponding third current on the output node; and
a control circuit coupled to receive a feedback signal based on a voltage present on the output node and configured to control respective states of transistors in the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter to cause the voltage on the output node to be maintained at a desired value.
2. The circuit of claim 1 , wherein the control circuit is configured to control switching sequences for the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter independently of one another.
3. The circuit of claim 1 , wherein the circuit includes a second two-level buck converter, wherein the control circuit is configured to control switching sequences for the first and second two-level buck converters such that their duty cycles are different from one another.
4. The circuit of claim 1 , wherein the circuit includes a second N-level buck converter, wherein the control circuit is configured to control switching sequences for the first and second N-level buck converters such that their duty cycles are different from one another.
5. The circuit of claim 1 , wherein the control circuit is configured to cause the first two-level buck converter to operate with a duty cycle of 50% and further configured to cause the first N-level buck converter to operate with a duty cycle that is not equal to 50%.
6. The circuit of claim 1 , further comprising a feedback circuit, wherein the control circuit is configured to control respective duty cycles of the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter based on the desired value of the voltage on the output node and a feedback voltage generated by the feedback circuit.
7. The circuit of claim 1 , further comprising a plurality of two-level buck converters including the first two-level buck converter.
8. The circuit of claim 1 , further comprising a plurality of N-level buck converters including the first N-level buck converter.
9. The circuit of claim 1 , wherein the N-level buck converter is a three-level buck converter.
10. The circuit of claim 9 , wherein the three-level buck converter includes:
a pull-up stack having a first and second transistors coupled in series between a first terminal of the second inductor and an input voltage node, the first transistor having a source terminal coupled to the input voltage node and the second transistor having a drain terminal coupled to the first terminal of the second inductor;
a pull-down stack having third and fourth transistors coupled in series between the first terminal of the second inductor and a ground node, the third transistor having a drain terminal coupled to the first terminal of the second inductor, and the fourth transistor having a source terminal coupled to the ground node; and
a capacitor coupled between the drain terminal of the first transistor and the drain terminal of the fourth transistor.
11. A method comprising:
providing a first current on an output node, wherein the first current is generated by a first two-level buck converter alternatively generating one of two voltage levels and converting the two voltage levels into the first current using a first inductor;
providing a second current on the output node, wherein the second current is generated by a first N-level buck converter generating one of N voltage levels in a predefined sequence and converting the N voltage levels into the second current using a second inductor, wherein N is an integer value of at least three
providing a third current on the output node using at least one M-level buck converter, wherein M is an integer value of three or more, and where M is not equal to N; and
a control circuit controlling respective duty cycles of transistors in each of the first two-level buck converter and the first N-level buck converter based on a desired output voltage and a feedback signal generated using a voltage present on the output node.
12. The method of claim 11 , further comprising controlling switching sequences for the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter independently of one another.
13. The method of claim 11 , further comprising the controlling switching sequences for the first two-level buck converter and a second two-level buck converter such that their duty cycles are different from one another.
14. The method of claim 11 , further comprising causing the first two-level buck converter to operate with a duty cycle of 50% the first N-level buck converter to operate with a duty cycle that is not equal to 50%.
15. The method of claim 11 , further comprising controlling respective duty cycles of the first two-level buck converter, the first N-level buck converter, and the at least one M-level buck converter based on desired value of the output voltage and a feedback voltage generated by a feedback circuit.
16. A system comprising:
a load circuit;
a hybrid voltage regulator configured to provide a supply voltage to the load circuit, the hybrid voltage regulator comprising:
a first two-level buck converter configured to provide a corresponding first current on an output node;
a first N-level buck converter configured to provide a corresponding second current on the output node, wherein N is an integer value greater than two;
a first M-level buck converter configured to provide a corresponding third current on the output node, wherein M is an integer value great than two and different from N; and
a control circuit configured to control switching sequences of transistors in the first two-level buck converter, the first N-level buck converter, and the first M-level buck converters, independently of one another, to generate the supply voltage at a desired voltage value on the output node.
17. The system of claim 16 , wherein the hybrid voltage regulator includes a second two-level buck converter, wherein the control circuit is configured to control respective switching sequences of the first and second two-level buck converters such that their respective duty cycles are different from one another.
18. The system of claim 16 , wherein the hybrid voltage regulator includes a second N-level buck converter, wherein the control circuit is configured to control respective switching sequences of the first and second N-level buck converters such that their respective duty cycles are different from one another.
19. The system of claim 16 , wherein the control circuit is configured to cause the first two-level buck converter to operate with a duty cycle of 50% and further configured to cause the first N-level buck converter to operate with a duty cycle that is not equal to 50%.
20. The system of claim 16 , wherein N=3, and wherein the first N-level buck converter includes:
a pull-up stack having a first and second transistors coupled in series between a first terminal of an inductor and an input voltage node, the first transistor having a source terminal coupled to the input voltage node and the second transistor having a drain terminal coupled to the first terminal of the inductor;
a pull-down stack having third and fourth transistors coupled in series between the first terminal of the inductor and a ground node, the third transistor having a drain terminal coupled to the first terminal of the inductor, and the fourth transistor having a source terminal coupled to the ground node; and
a capacitor coupled between the drain terminal of the first transistor and the drain terminal of the fourth transistor.