Dynamic traffic-aware interface queue switching among processor cores
Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.
1. A method comprising:
monitoring a data packet transfer rate at an interface queue and
based at least in part on the data packet transfer rate:
assigning the interface queue from a core of a first class to a core of a second class, or assigning the interface queue from a core of the second class to a core of the first class, wherein:
assigning the interface queue from the core of the first class to the core of the second class comprises disabling a bit associated with the interface queue in a bitmask associated with a core of the first class and enabling a bit in the bitmask associated with the interface queue of the core of the second class,
the bitmask comprises one or more bits,
a number of bits in the bitmask is based on a number of interface queues, and
a bit in the bitmask is associated with an interface queue.
2. The method of claim 1 , wherein
the first class comprises one or more cores operating at a first clock frequency,
the second class comprises one or more cores operating at a second clock frequency, and
the first clock frequency is higher than the second clock frequency.
3. The method of claim 1 , comprising detecting cores of the first class and cores of the second class prior to monitoring a data packet transfer rate at an interface queue.
4. The method of claim 1 , comprising assigning a packet processing thread to a core.
5. The method of claim 4 , comprising assigning the core to which the packet processing thread is assigned to the interface queue.
6. The method of claim 5 , wherein the packet processing thread reads one or more data packets from the interface queue assigned to the core to which the packet processing thread is assigned.
7. The method of claim 1 , comprising initializing a bitmask for a core.
8. The method of claim 7 , wherein assigning the interface queue from the core of the second class to the core of the first class comprises disabling a bit associated with the interface queue in the bitmask associated with the core of the second class and enabling a bit associated with the interface queue in the bitmask associated with the core of the first class.
9. At least one tangible non-transitory machine-readable medium comprising a plurality of instructions that in response to being executed by at least one processor having a plurality of cores cause the at least one processor to:
monitor a data packet transfer rate at an interface queue and
based at least in part on the data packet transfer rate:
assign the interface queue from a core of a first class to a core of a second class, or assign the interface queue from a core of the second class to a core of the first class, wherein:
assign the interface queue from the core of the first class to the core of the second class comprises disable a bit associated with the interface queue in a bitmask associated with a core of the first class and enable a bit in the bitmask associated with the interface queue of the core of the second class,
the bitmask comprises one or more bits,
a number of bits in the bitmask is based on a number of interface queues, and
a bit in the bitmask is associated with an interface queue.
10. The at least one tangible non-transitory machine-readable medium of claim 9 , comprising instructions that in response to being executed by the at least one processor, cause the at least one processor to: detect cores of the first class and cores of the second class prior to monitoring the data packet transfer rate.
11. The at least one tangible non-transitory machine-readable medium of claim 9 , comprising instructions that in response to being executed by the at least one processor, cause the at least one processor to assign a packet processing thread to a core.
12. The at least one tangible non-transitory machine-readable medium of claim 11 , comprising instructions that in response to being executed by the at least one processor, cause the at least one processor to assign a core to the interface queue.
13. The at least one tangible non-transitory machine-readable medium of claim 12 , comprising instructions that in response to being executed by the at least one processor, cause the at least one processor to: cause the packet processing thread to read one or more data packets from the interface queue assigned to the core to which the packet processing thread is assigned.
14. The at least one tangible non-transitory machine-readable medium of claim 9 , comprising instructions that in response to being executed by the at least one processor, cause the at least one processor to initialize a bitmask for a core.
15. The at least one tangible non-transitory machine-readable medium of claim 14 , wherein instructions to assign the interface queue from the core of the second class to the core of the first class comprise instructions to disable a bit associated with the interface queue in the bitmask associated with the core of the second class and enable a bit associated with the interface queue in the bitmask associated with the core of the first class.
16. A system comprising:
one or more cores; and
circuitry to monitor a data packet transfer rate at one or more interface queues, and based at least in part on the data packet transfer rate, assign an interface queue of the one or more interface queues from a core of a first class to a core of a second class, or to assign the interface queue from a core of the second class to a core of the first class, wherein
the one or more cores comprise the core of the first class and the core of the second class,
assign the interface queue from the core of the first class to the core of the second class comprises disable a bit associated with the interface queue in a bitmask associated with a core of the first class and enable a bit in the bitmask associated with the interface queue of the core of the second class,
the bitmask comprises one or more bits,
a number of bits in the bitmask is based on a number of interface queues, and
a bit in the bitmask is associated with an interface queue.
17. The system of claim 16 , wherein
the first class comprises one or more cores operating at a first clock frequency,
the second class comprises one or more cores operating at a second clock frequency, and
the first clock frequency is higher than the second clock frequency.
18. The system of claim 16 , comprising circuitry to detect cores of the first class and cores of the second class.
19. The system of claim 16 , comprising circuitry to assign a packet processing thread to a core.
20. The system of claim 19 , comprising circuitry to assign a core to the interface queue.
21. The system of claim 20 , wherein the packet processing thread is to read one or more data packets from the interface queue assigned to the core to which the packet processing thread is assigned.
22. The system of claim 16 , wherein the circuitry to monitor is to initialize a bitmask for a core.
23. The system of claim 22 , wherein the circuitry to monitor is to assign the interface queue from the core of the second class to the core of the first class by disable a bit associated with the interface queue in the bitmask associated with the core of the second class and enable a bit associated with the interface queue in the bitmask associated with the core of the first class.