System and method for counting fail bit and reading out the same
An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.
1. An apparatus comprising:
a memory array;
a counter circuit coupled to a terminal and configured to, during a test operation, update a count value in response to detection of an error, the error is detected based on a comparison between a first block of data and a consecutively read second block of data from the memory array, and between the second block of data and a consecutively read third block of data from the memory array; and
an input/output (I/O) circuit coupled to the counter circuit, wherein the I/O circuit includes a multiplexing circuit configured to provide the count value to a communication bus.
2. The apparatus of claim 1 further comprising a test compression logic coupled to the counter circuit and the multiplexing circuit, wherein the test compression logic is further configured to:
for the detection of an error, detect one or more errors in the blocks of data from the memory array during the test operation; and
provide test comparison data to the multiplexing circuit based on the one or more detected errors, wherein the test comparison data includes a pass/fail indication.
3. The apparatus of claim 2 , wherein the test compression logic is further configured to provide one or more error signals to the counter circuit, each error signal corresponds to a respective error of the detected one or more errors.
4. The apparatus of claim 3 , wherein the counter circuit comprises a counter configured to increment the count value responsive to each of the one or more error signals during the test operation.
5. The apparatus of claim 4 , wherein the counter circuit further comprises a counter increment control circuit coupled to the counter and configured to provide a full count signal to the counter.
6. The apparatus of claim 5 , wherein, responsive to the count value having reached a full count value, the counter increment control circuit is configured to provide the full count signal to cause the counter to maintain the count value.
7. The apparatus of claim 6 , wherein the counter comprises a ripple counter and the full count signal is provided to a clock line of the counter.
8. The apparatus of claim 2 , wherein the multiplexing circuit is configured to provide the test comparison data or the count value to the terminal responsive to a control signal.