IP Library › Granted Patent US 11,437,401
Granted Patent B2
US 11,437,401 · App. 17/203,352 · Granted Sep 6, 2022

3-dimensional NAND flash memory device, method of fabricating the same, and method of driving the same

Inventor: Woo Young Choi (Seoul, KR)
Assignees: SK hynix Inc.; SOGANG UNIVERSITY RESEARCH FOUNDATION
H01L27/11582H01L21/3105H01L29/408H01L29/40117H01L29/4234H01L29/513H01L29/517H01L29/518
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,437,401
App. No.
17/203,352
Granted
Sep 6, 2022
Kind
B2
Abstract

A 3-dimensional flash memory device and methods of fabricating and driving the same are provided. The device includes: a channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate; an information storing layer extending along a sidewall of the channel layer in the first direction; control gates each surrounding, the channel layer, with the information storing layer between the channel layer and the control gates; an insulating layer being between the control gates in the first direction and separating the control gates from each other; a fixed charge region disposed at an interface of the insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and a doped region induced by the fixed charge region and disposed at a surface of the channel layer facing the fixed charge region.

Claims (17)

1. A 3-dimensional NAND flash memory device, comprising,

a semiconductor channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate;

an information storing layer extending along a sidewall of the semiconductor channel layer in the first direction;

control gates each surrounding at least a portion of the semiconductor channel layer, with the information storing, layer between the semiconductor channel layer and the control gates;

an interlayer insulating layer being disposed between the control gates in the first direction and separating the control gates from each other;

a fixed charge region disposed at an interface of the interlayer insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and

an electrically doped region which is induced by the fixed charge region, and is disposed at a partial surface of the semiconductor channel, layer facing the fixed charge region.

2. The 3-dimensional NAND flash memory device of claim 1 , wherein the fixed charge region disposed at the interface of the interlayer insulating layer and the information storing layer includes a dangling bond of hydrogen molecules formed by a reaction of hydrogen bonding between hydrogen ions (H + ) and the interlayer insulating layer at the interface.

3. The 3-dimensional NAND flash memory device of claim 2 , wherein when the interlayer insulating layer includes silicon oxide, the fixed charge region has a Si—H bond.

4. The 3-dimensional NAND flash memory device of claim 1 , wherein the fixed charge region disposed in the portion of the information storing layer between the control gates is charged by fixed charges accumulated by a fringing field induced between the control gates and the semiconductor channel layer.

5. The 3-dimensional NAND flash memory device of claim 1 , further comprising a work function control layer having a work function smaller than that of the control gates on sidewalk of the control gates.

6. The 3-dimensional NAND flash memory device of claim 5 , wherein a thickness of the interlayer insulating layer may be greater than a thickness of the control gate.

7. The 3-dimensional NAND flash memory device of claim 1 , wherein the information storing layer includes a gate insulating layer on the semiconductor channel layer, a data storing layer on the gate insulating layer, and a blocking insulating layer on the data storing layer.

8. The 3-dimensional NAND flash memory device of claim 7 , wherein the data storing layer includes one selected from the group consisting of SiO 2 , SiON, Si 3 N 4 , SRN (Si rich nitride), HfO 2 , HfSiO, HfSiON, HfON, HfAlO, Al 2 O 3 , AlN, and a combination thereof.

9. The 3-dimensional NAND flash memory device of claim 7 , wherein the gate insulating layer includes one selected from the group consisting of SiO 2 , Si 3 N 4 , SiON, HfO 2 , HfSiO, Al 2 O 3 , ZrO 2 , and a combination thereof.

10. The 3-dimensional NAND flash memory device of claim 7 , wherein the blocking insulating layer includes one selected from the group consisting of Al 2 O 3 , SiO 2 , HfO 2 , ZrO 2 , Ta 2 O 5 , LaO, LaAlO, LaHfO, HfAlO, and a combination thereof.

11. The 3-dimensional NAND flash memory device of claim 1 , wherein the semiconductor channel layer has a cylindrical shape, and a core insulator is inserted into the semiconductor channel layer to form a semiconductor pillar.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2021
From: CHOI, WOO YOUNG
To: SK HYNIX INC.; SOGANG UNIVERSITY RESEARCH FOUNDATION
Reel/Frame 055621/0854 →
Priority Claims (1)
KR 10-2020-0031945 · Mar 16, 2020 · national
Continuity (1)
Related Publication 20210288070A1 · Sep 16, 2021