Robust state synchronization for stateful hash-based signatures

1. An apparatus, comprising:

a computer readable memory;

a signing facility comprising a plurality of hardware security modules; and

a state synchronization manager comprising processing circuitry to:

select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module;

assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence;

select a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module and a third hardware security module; and

assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence and a third synchronization counter sequence, wherein:

the first set of state synchronization counter sequences comprises a first plurality of counters selected from only integers which are evenly divisible by 3 and is assigned to the first hardware security module;

the second set of state synchronization counter sequences comprises a second plurality of counters selected from only integers which, when divided by 3, result in a remainder of 1, and is assigned to the second hardware security module; and

the third set of state synchronization counter sequences comprises a third plurality of counters selected from only integers which, when divided by 3, result in a remainder of 2, and is assigned to the third hardware security module.

2. The apparatus of claim 1 , wherein:

the first set of state synchronization counter sequences comprises a first plurality of counters selected from only even integers and is assigned to the first hardware security module; and

the second set of state synchronization counter sequences comprises a second plurality of counters selected from only odd integers and is assigned to the second hardware security module.

3. The apparatus of claim 2 , the signing facility further comprising signature processing circuitry to:

generate a first digital signature for a first message by applying a first hash function to a first string comprising at least one of a public key or a private key and a counter selected from the first plurality of counters.

4. The apparatus of claim 2 , the signing facility further comprising signature processing circuitry to:

generate a second digital signature for a second message by applying a second hash function to a second string comprising at least one of a public key or a private key and a counter selected from the first plurality of counters.

5. The apparatus of claim 1 , further comprising a load balancer to:

select one of the first hardware security module or the second hardware security module to generate a signature.

6. A computer-based method, comprising:

selecting, from a plurality of hardware security modules in a signing facility, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module;

assigning a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence;

selecting a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module and a third hardware security module; and

assigning a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence and a third synchronization counter sequence, wherein:

the first set of state synchronization counter sequences comprises a first plurality of counters selected from only integers which are evenly divisible by 3 and is assigned to the first hardware security module;

the second set of state synchronization counter sequences comprises a second plurality of counters selected from only integers which, when divided by 3, result in a remainder of 1, and is assigned to the second hardware security module; and

the third set of state synchronization counter sequences comprises a third plurality of counters selected from only integers which, when divided by 3, result in a remainder of 2, and is assigned to the third hardware security module.

7. The method of claim 6 , wherein:

the first set of state synchronization counter sequences comprises a first plurality of counters selected from only even integers and is assigned to the first hardware security module; and

the second set of state synchronization counter sequences comprises a second plurality of counters selected from only odd integers and is assigned to the second hardware security module.

8. The method of claim 7 , further comprising:

generating a first digital signature for a first message by applying a first hash function to a first string comprising at least one of a public key or a private key and a counter selected from the first plurality of counters.

9. The method of claim 7 , further comprising:

generating a second digital signature for a second message by applying a second hash function to a second string comprising at least one of a public key or a private key and a counter selected from the first plurality of counters.

10. The method of claim 6 , further comprising:

invoking a load balancer to select one of the first hardware security module or the second hardware security module to generate a signature.

11. A non-transitory computer readable medium comprising instructions which, when executed by a processor, configure the processor to:

select, from a plurality of hardware security modules in a signing facility, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module;

assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence;

select a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module and a third hardware security module; and

assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence and a third synchronization counter sequence, wherein:

the first set of state synchronization counter sequences comprises a first plurality of counters selected from only integers which are evenly divisible by 3 and is assigned to the first hardware security module;

the second set of state synchronization counter sequences comprises a second plurality of counters selected from only integers which, when divided by 3, result in a remainder of 1, and is assigned to the second hardware security module; and

the third set of state synchronization counter sequences comprises a third plurality of counters selected from only integers which, when divided by 3, result in a remainder of 2, and is assigned to the third hardware security module.

12. The computer readable medium of claim 11 , wherein:

the first set of state synchronization counter sequences comprises a first plurality of counters selected from only even integers and is assigned to the first hardware security module; and

the second set of state synchronization counter sequences comprises a second plurality of counters selected from only odd integers and is assigned to the second hardware security module.

13. The computer readable medium of claim 12 , comprising instructions to:

generate a first digital signature for a first message by applying a first hash function to a first string comprising at least one of a public key or a private key and a counter selected from the first plurality of counters.

14. The computer readable medium of claim 12 , comprising instructions to:

generate a second digital signature for a second message by applying a second hash function to a second string comprising at least one of a public key or a private key and a counter selected from the first plurality of counters.

15. The computer readable medium of claim 11 , comprising instructions to:

select one of the first hardware security module or the second hardware security module to generate a signature.