Driving circuit comprising redundant clock signal line and display panel
A driving circuit and a display panel are provided. In a driving circuit structure, a clock signal line group includes a plurality of clock signal lines, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines. A non-high frequency signal line is provided on two sides of the clock signal line group. A redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line, and a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line.
1. A driving circuit, comprising:
a signal generator;
a driving circuit unit;
a clock signal line group comprising a plurality of clock signal lines, wherein an input end of the clock signal line is electrically connected to the signal generator, and an output end of the clock signal line is electrically connected to the driving circuit unit, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines;
a non-high frequency signal line, wherein an input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is provided on two sides of the clock signal line group; and
a redundant clock signal line, wherein an input end of the redundant clock signal line is electrically connected to the signal generator; the redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line; a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line;
wherein the redundant clock signal line has a second pitch with an adjacent clock signal line, the second pitch is equal to the first pitch, a width of the redundant clock signal line is less than a width of the clock signal line, the non-high frequency signal line has a third pitch with an adjacent redundant clock signal line, and the third pitch is greater than the second pitch.
2. The driving circuit according to claim 1 , wherein a thickness of the redundant clock signal line and a thickness of the clock signal line are equal.
3. The driving circuit according to claim 1 , wherein material of the redundant clock signal line is the same as material of the clock signal line.
4. The driving circuit according to claim 1 , wherein the non-high frequency signal line is a low-frequency signal line or a DC signal line.
5. The driving circuit according to claim 4 , wherein an output end of the low-frequency signal line is electrically connected to the driving circuit unit or a common electrode.
6. A display panel, comprising:
a driving circuit disposed in a non-display area of the display panel, wherein the driving circuit comprising:
a signal generator;
a driving circuit unit;
a clock signal line group comprising a plurality of clock signal lines, wherein an input end of the clock signal line is electrically connected to the signal generator, and an output end of the clock signal line is electrically connected to the driving circuit unit, the clock signal lines are arranged side by side, and there is a first pitch between two adjacent clock signal lines;
a non-high frequency signal line, wherein an input end of the non-high frequency signal line is electrically connected to the signal generator, and the non-high frequency signal line is provided on two sides of the clock signal line group; and
a redundant clock signal line, wherein an input end of the redundant clock signal line is electrically connected to the signal generator; the redundant clock signal line is disposed between the clock signal line group and the non-high frequency signal line; a frequency and an amplitude of a signal received by the redundant clock signal line are the same as a frequency and an amplitude of a signal received by the clock signal line;
wherein the redundant clock signal line has a second pitch with an adjacent clock signal line, the second pitch is equal to the first pitch, a width of the redundant clock signal line is less than a width of the clock signal line, the non-high frequency signal line has a third pitch with an adjacent redundant clock signal line, and the third pitch is greater than the second pitch.
7. The display panel according to claim 6 , wherein a thickness of the redundant clock signal line and a thickness of the clock signal line are equal.
8. The display panel according to claim 6 , wherein material of the redundant clock signal line is the same as material of the clock signal line.
9. The display panel according to claim 6 , wherein the non-high frequency signal line is a low-frequency signal line or a DC signal line.
10. The display panel according to claim 9 , wherein an output end of the low-frequency signal line is electrically connected to the driving circuit unit or a common electrode.