IP Library › Granted Patent US 11,444,162
Granted Patent B2
US 11,444,162 · App. 17/159,423 · Granted Sep 13, 2022

Backside contact with air spacer

Inventors: Chen-Ming Lee (Taoyuan County, TW); Wei-Yang Lee (Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L29/401H01L21/283H01L21/32135H01L29/4175H01L29/66795H01L29/78696
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Quick Facts
Patent No.
US 11,444,162
App. No.
17/159,423
Granted
Sep 13, 2022
Kind
B2
Abstract

A method includes performing a first etching process on a backside of a substrate to expose a dummy contact structure, performing a first deposition process to deposit a first dielectric layer around the dummy contract structure, performing a second deposition process to deposit an oxide layer on the first dielectric layer, removing the dummy contract structure to form a trench, depositing a sacrificial layer on sidewalls of the trench, depositing a second dielectric layer on the sacrificial layer, filling the trench with a conductive material, and removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

Claims (38)

1. A method comprising:

performing a first etching process on a backside of a substrate to expose a dummy contact structure;

performing a first deposition process to deposit a first dielectric layer around the dummy contact structure;

performing a second deposition process to deposit an oxide layer on the first dielectric layer;

removing the dummy contact structure to form a trench;

depositing a sacrificial layer on sidewalls of the trench;

depositing a second dielectric layer on the sacrificial layer;

filling the trench with a conductive material; and

removing the sacrificial layer to form an air spacer between the first dielectric layer and the second dielectric layer.

2. The method of claim 1 , wherein the first dielectric layer comprises silicon nitride.

3. The method of claim 1 , wherein the second dielectric layer comprises silicon nitride.

4. The method of claim 1 , wherein the sacrificial layer comprises silicon.

5. The method of claim 4 , wherein the sacrificial layer is formed using a thermal deposition process.

6. The method of claim 1 , wherein removing the dummy contact structure comprises a dry etching process.

7. The method of claim 1 , further comprising, forming a seal on top of the air spacer.

8. The method of claim 7 , wherein the seal comprises a dielectric material.

9. The method of claim 1 , further comprising, before filling the trench implanting a dopant into a source/drain region exposed at a bottom of the trench.

10. A method comprising:

applying an etching process to remove a dummy contact structure from a backside of a substrate and expose a source/drain region at a bottom of a trench;

depositing a sacrificial layer on sidewalls of the trench;

depositing a dielectric layer on the sacrificial layer;

filling the trench with a conductive material; and

removing the sacrificial layer.

11. The method of claim 10 , further comprising, after depositing the dielectric layer on the sacrificial layer, applying a dry etching process to remove portions of the dielectric layer from the bottom of the trench.

12. The method of claim 10 , further comprising, rounding top corners of the trench before depositing the sacrificial layer.

13. The method of claim 10 , further comprising, before removing the dummy contact structure, removing a silicon material from around the dummy contact structure.

14. The method of claim 13 , further comprising, before removing the dummy contact structure, forming an oxide layer around the dummy contact structure.

15. The method of claim 10 , wherein removing the sacrificial layer leaves an air gap adjacent to the dielectric layer.

16. The method of claim 15 , further comprising, depositing a seal to close the air gap.

17. The method of claim 10 , wherein the sacrificial layer is formed using a thermal Chemical Vapor Deposition (CVD) process.

18. A semiconductor structure comprising:

a substrate having a frontside and a backside;

a transistor formed on the frontside of the substrate, the transistor comprising a source/drain region;

a contact extending from a bottom of the source/drain region to the backside of the substrate, wherein the contact is in direct contact with the source/drain region; and

a first dielectric layer positioned along sides of the contact;

an air gap positioned between the first dielectric layer and a second dielectric layer.

19. The semiconductor structure of claim 18 , further comprising, a seal structure formed on a bottom of the air gap, wherein a portion of the seal structure is between the first dielectric layer and the second dielectric layer.

20. The semiconductor structure of claim 18 , wherein the first dielectric layer comprises silicon nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2021
From: LEE, CHEN-MING; LEE, WEI-YANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 056197/0978 →
Continuity (1)
Related Publication 20220238659A1 · Jul 28, 2022
Cited By (1)
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