Inner spacer liner
The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.
1. A semiconductor device, comprising:
a first source/drain feature and a second source/drain feature over a substrate;
a plurality of channel members extending between the first source/drain feature and the second source/drain feature;
a plurality of inner spacer features interleaving the plurality of channel members;
a gate structure wrapping around each of the plurality of channel members; and
a semiconductor liner sandwiched directly between a sidewall of the gate structure and each of the plurality of inner spacer features.
2. The semiconductor device of claim 1 , wherein the semiconductor liner is sandwiched between each of the plurality of inner spacer features and an adjacent channel member of the plurality of channel members.
3. The semiconductor device of claim 1 , wherein the semiconductor liner comprises silicon (Si).
4. The semiconductor device of claim 3 , wherein the first source/drain feature comprises silicon (Si) and an n-type dopant.
5. The semiconductor device of claim 3 , wherein the first source/drain feature comprises silicon germanium (SiGe) and a p-type dopant.
6. The semiconductor device of claim 1 ,
wherein the first source/drain feature comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer,
wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant,
wherein a concentration of the dopant in the second epitaxial layer is greater than a concentration of the dopant in the first epitaxial layer.
7. The semiconductor device of claim 6 , wherein the first epitaxial layer is in contact with the semiconductor liner and the second epitaxial layer is spaced apart from the semiconductor liner.
8. A semiconductor structure, comprising:
a first epitaxial feature and a second epitaxial feature;
a plurality of nanostructures extending between the first epitaxial feature and the second epitaxial feature along a first direction;
a plurality of inner spacer features interleaving the plurality of nanostructures;
a gate structure wrapping around each of the plurality of nanostructures; and
a silicon liner sandwiched directly between the gate structure and each of the plurality of inner spacer features along the first direction,
wherein the silicon liner is in contact with the first epitaxial feature and the second epitaxial feature.
9. The semiconductor structure of claim 8 , wherein the silicon liner is sandwiched between each of the plurality of inner spacer features and an adjacent nanostructure of the plurality of nanostructures.
10. The semiconductor structure of claim 8 , wherein the plurality of nanostructures are coupled together by the silicon liner.
11. The semiconductor structure of claim 8 ,
wherein the first epitaxial feature comprises a first epitaxial layer and a second epitaxial layer,
wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant,
wherein a concentration of the dopant in the second epitaxial layer is greater than a concentration of the dopant in the first epitaxial layer.
12. The semiconductor structure of claim 11 , wherein the first epitaxial layer is in contact with the silicon liner and the second epitaxial layer is spaced apart from the silicon liner.
13. The semiconductor structure of claim 11 ,
wherein the first epitaxial feature comprises silicon (Si),
wherein the dopant is an n-type dopant.
14. The semiconductor structure of claim 11 ,
wherein the first epitaxial feature comprises silicon germanium (SiGe),
wherein the dopant is a p-type dopant.
15. A method, comprising:
forming a stack over a substrate, wherein the stack comprises a plurality of silicon layers interleaved by a plurality of silicon germanium layers;
forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure comprising a channel region and a source/drain region;
recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers;
selectively and partially recessing the plurality of silicon germanium layers to form a plurality of inner spacer recesses;
depositing a semiconductor layer over the plurality of inner spacer recesses;
depositing an inner spacer layer over the semiconductor layer;
etching back the semiconductor layer and the inner spacer layer to form a plurality of inner spacer features in the plurality of inner spacer recesses;
after the etching back, forming a source/drain feature in the source/drain trench;
releasing the plurality of silicon layers in the channel region as a plurality of channel members; and
forming a gate structure around each of the plurality of channel members.
16. The method of claim 15 , where the depositing of the semiconductor layer comprises epitaxially depositing a silicon layer.
17. The method of claim 15 , wherein after the depositing of the semiconductor layer, the semiconductor layer in contact with the plurality of silicon germanium layers.
18. The method of claim 15 , wherein the forming of the source/drain feature comprises:
depositing a first epitaxial layer; and
depositing a second epitaxial layer over the first epitaxial layer.
19. The method of claim 18 , wherein the depositing of the first epitaxial layer comprises depositing the first epitaxial layer in contact with the silicon layers and the semiconductor layer.
20. The method of claim 19 , wherein the second epitaxial layer is spaced apart from the semiconductor layer.