Leakage current reduction in polysilicon-on-active-edge structures
Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.
1. A transistor structure comprising:
one or more active devices; and
at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices, wherein:
a first gate structure of the at least one dummy device comprises a positive work function metal layer and a negative work function metal layer; and
a second gate structure of the one or more active devices comprises a negative work function metal layer and lacks a positive work function metal layer.
2. The transistor structure of claim 1 , wherein the at least one dummy device comprises a polysilicon on oxide-defined (OD) edge (PODE) structure.
3. The transistor structure of claim 1 , wherein a first gate structure of the at least one dummy device has a smaller width than a second gate structure of one of the active devices.
4. The transistor structure of claim 3 , wherein:
the first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
the second gate structure of the one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.
5. The transistor structure of claim 1 , wherein:
a first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
a second gate structure of one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.
6. The transistor structure of claim 1 , wherein a first gate structure of the at least one dummy device has a greater width than a second gate structure of one of the active devices.
7. The transistor structure of claim 6 , wherein:
the first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
the second gate structure of the one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.
8. The transistor structure of claim 6 , wherein an active area disposed underneath the first gate structure comprises a first portion having a first width and a second portion having a second width that is less than the first width.
9. The transistor structure of claim 8 , wherein a length of the first portion of the active area disposed underneath the first gate structure is less than a length of the second portion of the active area disposed underneath the first gate structure.
10. The transistor structure of claim 1 , wherein a gate structure of the at least one dummy device overhangs and extends beyond three consecutive edges of an active area.
11. The transistor structure of claim 1 , wherein an active area disposed underneath a gate structure of the at least one dummy device comprises a first portion having a first width and a second portion having a second width that is less than the first width.
12. The transistor structure of claim 11 , wherein a length of the first portion of the active area disposed underneath the gate structure of the at least one dummy device is greater than a length of the second portion of the active area disposed underneath the gate structure of the at least one dummy device.
13. The transistor structure of claim 1 , further comprising:
a plurality of parallel channel structures;
one or more gate conductors, each gate conductor being disposed at least above the plurality of parallel channel structures and having a longitudinal axis disposed perpendicular to the plurality of parallel channel structures, wherein intersections of the one or more gate conductors and the plurality of parallel channel structures form the one or more active devices; and
at least one dummy structure disposed at the edge of the transistor structure, disposed at least above the plurality of parallel channel structures, and having a longitudinal axis disposed perpendicular to the plurality of parallel channel structures, wherein intersections of the at least one dummy structure and the plurality of parallel channel structures form the at least one dummy device.
14. The transistor structure of claim 13 , wherein the plurality of parallel channel structures comprise a plurality of parallel fins and wherein the one or more active devices comprise one or more fin field-effect transistors (finFETs).
15. The transistor structure of claim 13 , wherein the plurality of parallel channel structures define an oxide-defined (OD) area and wherein the at least one dummy device comprises a polysilicon on OD edge (PODE) structure.
16. The transistor structure of claim 1 , wherein:
the at least one dummy device is configured to have no active function; and
the at least one dummy device comprises a first gate structure that includes one or more different layers compared to a second gate structure of the one or more active devices.
17. A method for fabricating a transistor structure, comprising:
forming one or more active devices; and
forming at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices, wherein:
a first gate structure of the at least one dummy device comprises a positive work function metal layer and a negative work function metal layer; and
a second gate structure of the one or more active devices comprises a negative work function metal layer and lacks a positive work function metal layer.
18. The method of claim 17 , wherein:
a first gate structure of the at least one dummy device has a smaller width than a second gate structure of one of the active devices;
the first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
the second gate structure of one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.