IP Library › Granted Patent US 11,449,422
Granted Patent B2
US 11,449,422 · App. 16/944,944 · Granted Sep 20, 2022

Memory controller and operating method thereof

Inventor: Seok Jun Lee (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F12/0804G06F2212/608G11C16/0483
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Quick Facts
Patent No.
US 11,449,422
App. No.
16/944,944
Granted
Sep 20, 2022
Kind
B2
Abstract

There are provided a memory controller for managing meta data and an operating method of the memory controller. The memory controller includes: a buffer memory for storing meta data used to control an operation of a memory device; and a central processing unit for updating the meta data stored in the buffer memory whenever the operation of the memory device is controlled. The central processing unit may transmit the meta data stored in the buffer memory to a host at a first frequency, and transmit the meta data stored in the buffer memory to the memory device at a second frequency lower than the first frequency.

Claims (32)

1. A memory controller comprising:

a buffer memory configured to store meta data used to control an operation of a memory device;

a central processing unit configured to:

update the meta data stored in the buffer memory based on whether the operation of the memory device is controlled,

transmit the meta data stored in the buffer memory to a host at a first frequency, and

transmit the meta data stored in the buffer memory to the memory device at a second frequency lower than the first frequency; and

a voltage monitor configured to determine whether voltage abnormality has occurred in a voltage supplied to the memory controller while the meta data stored in the buffer memory is being transmitted to the host.

2. The memory controller of claim 1 , wherein the central processing unit controls the second frequency based on information on power stability of the host.

3. The memory controller of claim 2 , wherein the central processing unit increases the second frequency as the power stability becomes lower.

4. The memory controller of claim 2 , wherein information on the power stability includes at least one of residual amount of power of a battery of the host, degree of aging of the battery, or temperature of the host.

5. The memory controller of claim 1 , wherein the central processing unit transmits the meta data stored in the buffer memory to the host whenever user data provided from the host to the memory device is a first size, and transmits the meta data stored in the buffer memory to the memory device whenever user data is a second size greater than the first size.

6. The memory controller of claim 1 , wherein the central processing unit transmits, to the host, a signal representing that the transmission of the meta data stored in the buffer memory has been completed after the meta data is transmitted to the host, according to determination of the voltage monitor that voltage abnormality has not occurred.

7. The memory controller of claim 1 , wherein the central processing unit retransmits the meta data stored in the buffer memory to the host, according to determination of the voltage monitor that voltage abnormality has occurred.

8. The memory controller of claim 1 , wherein, during power-on after power-off, the central processing unit selects latest meta data from meta data received from the host and meta data received from the memory device, and controls the operation of the memory device, based on the selected meta data.

9. The memory controller of claim 1 , wherein the meta data includes at least one of address mapping information, read count information, open block information, or valid page information.

10. A method for operating a memory controller, the method comprising:

updating meta data stored in a buffer memory based on whether an operation of a memory device is controlled;

transmitting the meta data stored in the buffer memory to a host at a first frequency;

transmitting the meta data stored in the buffer memory to the memory device at a second frequency lower than the first frequency; and

determining whether voltage abnormality has occurred in a voltage supplied to the memory controller while the meta data stored in the buffer memory is being transmitted to the host.

11. The method of claim 10 , further comprising controlling the second frequency based on information on power stability of the host.

12. The method of claim 11 , wherein the controlling of the second frequency includes increasing the second frequency as the power stability becomes lower.

13. The method of claim 11 , wherein the information on the power stability includes at least one of residual amount of power of a battery of the host, degree of aging of the battery, or temperature of the host.

14. The method of claim 10 ,

wherein the transmitting of the meta data to the host at the first frequency includes transmitting the meta data stored in the buffer memory to the host whenever user data provided from the host to the memory device is a first size,

wherein the transmitting of the meta data to the memory device at the second frequency includes transmitting the meta data stored in the buffer memory to the memory device whenever user data is a second size greater than the first size.

15. The method of claim 10 , further comprising transmitting, to the host, a signal representing that the transmission of the meta data stored in the buffer memory has been completed after the meta data is transmitted to the host, according to determination that voltage abnormality has not occurred.

16. The method of claim 10 , further comprising retransmitting the meta data stored in the buffer memory to the host, according to determination that voltage abnormality has occurred.

17. The method of claim 10 , further comprising:

selecting latest meta data from meta data received from the host and meta data received from the memory device, during power-on after power-off; and

controlling the operation of the memory device based on the selected meta data.

18. The method of claim 10 , wherein the meta data includes at least one of address mapping information, read count information, open block information, or valid page information.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2020
From: LEE, SEOK JUN
To: SK HYNIX INC.
Reel/Frame 053371/0178 →
Priority Claims (1)
KR 10-2020-0016606 · Feb 11, 2020 · national
Continuity (1)
Related Publication 20210248075A1 · Aug 12, 2021